No abstract

In this paper a simplified hardware implementation of a CNN softmax-like layer is proposed. Initially the softmax activation function is analyzed in terms of required numerical accuracy and certain optimizations are proposed. A proposed adaptable hardware architecture is evaluated in terms of the introduced error due to the proposed softmax-like function. The proposed architecture can be adopted to the accuracy required by the application by retaining or eliminating certain terms of the approximation thus allowing to explore accuracy for complexity trade-offs. Furthermore, the proposed circuits are synthesized in a 90 nm 1.0 V CMOS standard-cell library using Synopsys Design Compiler. Comparisons reveal that significant reduction is achieved in area×delay and power×delay products for certain cases, respectively, over prior art. Area and power savings are achieved with respect to performance and accuracy.

No abstract

In this paper, the potential of reducitq power dissiputiun in u digital system using the Logarithmic Number System (LNS) is investigated. To provide a quantitative measure ofpower savings, the equivalence of an LNS to a linear fixed-point system is initially explored. The bit assertion activity uf an LNS encoded signul is studied ,fbr both unifi)rtn and correlated Gaussian inputs. It is shown that LNS reduces the uverage bit assertion probability by more than 50%. in certain cases, over an equivalent linear representation. Finally, the impact qf LNS on the hardware urchitecture and, by meum of that, to power dissipation, is discussed. Ir is,foutul that the uveruge number qf Iugic lransitions is reduced by severul times, f i x certain arithmetic operations and word lengths, thus compensuting the pi~wer-di.~.~iputii)n overheud due to the unavoidable linear-to-logarithmic and bgarithmic-tolineur conversion.

No abstract