In this paper a time synchronization algorithm for IEEE 802.11a/g OFDM-WLAN standard is presented and some modifications are proposed to simplify its implementation without sacrifice its performance. To evaluate its feasibility this algorithm is compared with others found in the literature. The comparison of performance has been carried out by simulation in multipath channels, at low signal to noise ratios and with carrier frequency offset. It is shown that the proposed solution has a better performance and a lower computational cost.
Abstract-A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of messages sent to the variable node. Additionally, the memory resources from the layered architecture are reduced. The proposed decoder was implemented for the (2304,2048) NB-LDPC code over GF(16) on a Virtex-7 FPGA and in a 90 nm CMOS process. Our implementation outperforms state-of-the-art NB-LDPC decoder implementations for both technologies, achieving a throughput of 630 and 965 Mbps, respectively.
A VLSI architecture for the generalized bit-flipping decoding algorithm for non-binary low-density parity-check codes is proposed in this paper. The tentative decoding steps of the algorithm have been modified to avoid computing and storing a matrix of dimension N × 2 q , for a code (N, K) over GF(2 q ), reducing its complexity with a minimal penalization of its performance, less than 0.05 dB compared with the original algorithm. The architecture was synthesized using a 90 nm standard cell library, for the (837, 723) non-binary code over GF(2 5 ), requiring 590220 xor gates and achieving a throughput of 89 Mbps. Additionally, it was implemented in a Virtex-VI FPGA device with a cost of 4070 slices and a throughput of 44.6 Mbps.
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