Record power added efficiency of bipolar power transistors for low voltage wireless applications

Rijs, F. van; Visser, H.A.; Magnee, P.H.C.

doi:10.1109/iedm.1998.746513

Cited by 13 publications

(5 citation statements)

References 6 publications

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“…The buried oxide in the SOI structure reduces capacitive coupling to the substrate, which improves power efficiency [5]. The SOI buried oxide also provides improved isolation between adjacent circuits [6], making it attractive for highly integrated power amplifiers in which substrate cross talk is a concern.…”

Section: Ilicon-on-insulator (Soi) Mos Technology Hasmentioning

confidence: 99%

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Experimental comparison of RF power LDMOSFETs on thin-film SOI and bulk silicon

Fiorenza

Alamo

2002

IEEE Trans. Electron Devices

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Abstract-We have simultaneously fabricated RF power LDMOSFETs on thin-film SOI and bulk silicon wafers. This work compares their DC current-voltage ( -), capacitance-voltage ( -), -parameter, and 1.9-GHz load-pull characteristics and explains differences between them. The SOI LDMOSFET performance is shown to be largely similar to the performance of an equivalent bulk silicon LDMOSFET, but there are important differences. The SOI LDMOSFET has moderately lower on-state breakdown voltage due to increased body resistance. It also has significantly improved power-added efficiency due to reduced parasitic pad losses.Index Terms-Power MOSFET, silicon-on-insulator (SOI) technology.

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Section: Ilicon-on-insulator (Soi) Mos Technology Hasmentioning

confidence: 99%

“…The n source and drain regions were formed by a masked implant of dose 5 10 cm and energy 25 KeV. The n implant mask defined the length of the n region.…”

Section: Device Fabricationmentioning

confidence: 99%

Experimental comparison of RF power LDMOSFETs on thin-film SOI and bulk silicon

Fiorenza

Alamo

2002

IEEE Trans. Electron Devices

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“…SOI technology offers a large number of advantages in terms of reduced capacitances, less cross-talk and high integration density. The buried oxide reduces capacitive coupling to the substrate, which improves the power efficiency [2], and also provides good isolation between low and high power stages [3]. Finally, SOI wafers with high resistivity substrates allow the monolithic integration of high Q inductors.…”

Section: Introductionmentioning

confidence: 99%

A numerical study of field plate configurations in RF SOI LDMOS transistors

Cortés

Roig

Flores

et al. 2006

Solid-State Electronics

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“…Among these advantages are reduced parasitic capacitances and excellent isolation among devices integrated on a single chip. 1,2) On the other hand, among different structures proposed for HF power devices lateral double-diffused metal-oxide-semiconductor field-effect transistors (LDMOSFETs) are highly preferred due to their compatibility with conventional VLSI technology and reduced steps in the fabrication process. 3,4) LDMOSFET is a combination of the conventional MOSFET and a series resistance between the channel and the drain contact.…”

Section: Introductionmentioning

confidence: 99%

Performance Improvement of Partially Silicon-on-Insulator Lateral Double-Diffused Metal–Oxide–Semiconductor Field-Effect Transistors Using Doping-Engineered Drift Region

Mohammadi

Afzali-Kusha

2012

Jpn. J. Appl. Phys.

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In this paper, we investigate the characteristics of a drift region engineered lateral double-diffused metal–oxide–semiconductor field-effect transistor (LDMOSFET) based on partially silicon on insulator (PSOI) technology. The structure, which is called DEPSOI (drift region engineered PSOI), has a drift region with two different doping density levels. The structure only needs one additional fabrication mask, compared to the conventional power PSOI device. In the drift region, a new peak is formed in the lateral electric field distribution at the boundary between the drift areas, which leads to a flatter electric field profile and subsequently a higher breakdown voltage (BV) compared to those of a conventional device. The results show that the DEPSOI LDMOSFET has a BV which is about 64% more than that of an optimized conventional PSOI LDMOSFET with the same dimension. The use of two different doping density levels allows simultaneous optimization of different device parameters. Having one part of drift region with a higher doping density level leads to an improvement of the on-state resistance (R on). Finally, DEPSOI LDMOSFET has a superior heat dissipation property than that of the conventional LDMOSFET structures. The effects of varying different physical parameters of the structure on the characteristics of the transistor are also studied.

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Record power added efficiency of bipolar power transistors for low voltage wireless applications

Cited by 13 publications

References 6 publications

Experimental comparison of RF power LDMOSFETs on thin-film SOI and bulk silicon

Experimental comparison of RF power LDMOSFETs on thin-film SOI and bulk silicon

A numerical study of field plate configurations in RF SOI LDMOS transistors

Performance Improvement of Partially Silicon-on-Insulator Lateral Double-Diffused Metal–Oxide–Semiconductor Field-Effect Transistors Using Doping-Engineered Drift Region

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