Record-high performance 32 nm node pMOSFET with advanced Two-step recessed SiGe-S/D and stress liner technology

Abstract

Two-step recessed SiGe-S/D pMOSFET [1] has been optimized with a combination of compressive stress liner. Optimization on source and drain overlap, defect control and elevated SiGe-S/D structure are discussed experimentally. As a result of the careful optimization, record high drive current of 714 �A/�m at Vdd=1.0V, Ioff =100 nA/�m at 24 nm gate length, is demonstrated.

eSiGe Global and Micro Loading Effect Study in High Performance 45nm CMOS Technology

“…Minimize global and micro loading effect eSiGe is a very complex process module, with many factors such as recess profile, Ge concentration, doping, channel proximity which will impact final PMOS performance (2)(3)(4)9). In our work, we found SiGe thickness is a very sensitive parameter which will affect PMOS device performance.…”

“…There has been an explosive increasing of interest in embedded SiGe epitaxial applications on the recessed source/drain (S/D) areas beyond 90nm CMOS process during the past years (1)(2)(3)(4). Because eSiGe help us to create a compressive strained channel to enhance carrier mobility, and makes it possible to fabricate a faster transistor without shrinkage of channel length.…”

Selective epitaxy growth of Si1−xGex layers for MOSFETs and FinFETs

“…Yasutake et al [67] presented a two-step recessed for S/D region with an addition to stress liner to create 1.7 GPa strain for MOSFETs. The results showed the short channel effect as well as the drive current is remarkably improved by this design.…”

Design and Optimization of Gate Sidewall Spacers to Achieve 45 nm Ground Rule for High-Performance Applications

“…As we have previously described, SW2 acts as an offset to control the proximity of eSiGe to the channel. We can enhance channel strain by using a closer proximity of eSiGe; 11,12) however, this change also deteriorates the threshold voltage (V th ) roll-off characteristics in the case of using in-situ B-doped SiGe. Figure 6 shows the dependence of V th on L g for different SW2 deposition thicknesses from the control to 10-nm less thickness for both N-and PFETs.…”