Realization of Unidirectional Planar GaAs Nanowires on GaAs (110) Substrates

Dowdy, Ryan; Walko, Donald A.; Fortuna, Seth A.; Li, Xiuling

doi:10.1109/led.2012.2186115

Cited by 33 publications

(40 citation statements)

References 14 publications

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“…It should be noted, that growth of planar NWs along the substrate surface is a subfield within NW growth [44][45][46][47]. However, growth of NWs in general implies a continuous supply of group III as well as group V. Here we have no intentional source of group III material on during our annealing experiments.…”

Section: A Annealing Of Au Nanoparticles On Gaas 111b and 100 Smentioning

confidence: 99%

Annealing of Au, Ag and Au–Ag alloy nanoparticle arrays on GaAs (100) and (111)B

et al. 2017

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Part of developing new strategies for fabrications of nanowire structures involves in many cases the aid of metal nanoparticles (NPs). It is highly beneficial if one can define both diameter and position of the initial NPs and make well-defined nanowire arrays. This sets additional requirement on the NPs with respect to being able to withstand a pre-growth annealing process (i.e. de-oxidation of the III-V semiconductor surface) in an epitaxy system.Recently, it has been demonstrated that Ag may be an alternative to using Au NPs as seeds for particle-seeded nanowire fabrication. This work brings light onto the effect of annealing of Au, Ag and Au-Ag alloy NP arrays in two commonly used epitaxial systems, the Molecular Beam Epitaxy (MBE) and the Metalorganic Vapor Phase Epitaxy (MOVPE). The NP arrays are fabricated with the aid of Electron Beam Lithography on GaAs 100 and 111B wafers and the evolution of the NPs with respect to shape, size and position on the surfaces 2 are studied after annealing using Scanning Electron Microscopy (SEM). We find that while the Au NP arrays are found to be stable when annealed up to 600 °C in a MOVPE system, a diameter and pitch dependent splitting of the particles are seen for annealing in a MBE system. The Ag NP arrays are less stable, with smaller diameters (≤ 50 nm) dissolving during annealing in both epitaxial systems. In general, the mobility of the NPs is observed to differ between the two the GaAs 100 and 111B surfaces. While the initial pattern is found be intact on the GaAs 111B surface for a particular annealing process and particle type, the increased mobility of the NP on the 100 may influence the initial pre-defined positions at higher annealing temperatures. The effect of annealing on Au-Ag alloy NP arrays suggests that these NP can withstand necessary annealing conditions for a complete de-oxidation of GaAs surfaces.

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Section: A Annealing Of Au Nanoparticles On Gaas 111b and 100 Smentioning

confidence: 99%

Annealing of Au, Ag and Au–Ag alloy nanoparticle arrays on GaAs (100) and (111)B

et al. 2017

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“…[1]- [4]. This implies that the the roughness on the GaAs/oxide interfaces examined in this work is does not impact device performance too negatively.…”

Section: Device Characteristicsmentioning

confidence: 92%

Radiation Effects in III-V Nanowire Devices

Brueck¹

2016

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Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden to Department of Defense, Washington Headquarters Services, Directorate for Information Operations and Reports (0704-0188), 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to any penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. PLEASE DO NOT RETURN YOUR FORM TO THE ABOVE ADDRESS. REPORT DATE (DD-MM-YYYY)2. REPORT TYPE 3. DATES COVERED (From -To) 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S) 5d. PROJECT NUMBER 5e. TASK NUMBER 5f. WORK UNIT NUMBER Distribution Statement A. Approved for public release; distribution is unlimited. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) 8. PERFORMING ORGANIZATION REPORT NUMBER SPONSORING / MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR'S ACRONYM(S) SPONSOR/MONITOR'S REPORT NUMBER(S)12The top-down fabrication of an in-plane nanowire (NW) GaAs metal-oxide-semiconductor field-effect transistor (MOSFET) by focused-ion beam (FIB) etching and chemical oxidation is reported. The device has a semiconductor-on-insulator structure with an n+-GaAs/Al2O3 layer stack implemented by lateral hydrolyzation oxidation. A 2 micron-long channel having an effective cross section ~70 x 220 nm is directly fabricated into the n+-GaAs layer by FIB etching. The channel is electronically isolated from the substrate by the Al2O3 layer and is effectively an in-plane NW epitaxially connected to the source and drain for a planar MOSFET within a single layer. The NW channel is surrounded by an ~15 nm-thick gate oxide. IntroductionNanowires are a potential structure for replacing planar CMOS in next generation electronics. Most investigations have relied on vertical growth (often with wire-to-wire variations in linewidths and random positioning) based on vapor-liquid-solid (VLS) catalyzed growth. Moving this technology from single transistor measurements to the construction of circuits with billions of transistors to complement existing integrated circuit technologies would require pick and place technologies to which are inherently slow and non-scalable. An attractive alternative that has received much less attention is the top-down fabrication of in-plane nanowires where the relative locations and interconnections are defined by lithographic processes. We are exploring the capabilities of III-V semiconductors in a SOI geometry which are well-developed technologies capability of scaling to dense circuit structures ...

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“…Note in Figure 9.10(b) that the <110> GaAs planar nanowires grow bidirectionally in [0-11] and [01-1] directions, which match with the surface projections of the two equivalent <111> B directions above the (100) GaAs substrates (Figure 9.8(c)-(d)). Since there is only one <111> B direction above the (110) GaAs substrate (Figure 9.8(e)-(f)), unidirectional [00-1] GaAs planar nanowires were achieved by using (110) GaAs substrates (Figure 9.12(b)) [129]. Figure 9.12(a) shows GaAs planar nanowires grown along the two nonparallel surface projections of <111> B directions on (100) GaAs substrates offcut by 10 toward the [0-10] direction.…”

Section: Planar Nanowiresmentioning

confidence: 99%