Radix-4 and radix-8 booth encoded interleaved modular multipliers over general F&lt;inf&gt;p&lt;/inf&gt;

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

Wang

Scott³

2015

Self Cite

Modular multiplication is a core operation in all public key based cryptosystems. The performance of these cryptosystems can be enhanced substantially by incorporating an optimized modular multiplier. This paper presents serial and parallel radix-4 modular multipliers based on interleaved multiplication algorithm and Montgomery power laddering technique. A serial radix-4 interleaved modular multiplier provides 50% reduction in the required clock cycles. In addition to the reduction in clock cycles, a parallel modular multiplier maintains a critical path delay comparable to the bit serial interleaved multipliers. The proposed designs are implemented in Verilog HDL and synthesized targeting virtex-6 FPGA platform using Xilinx ISE 14.2 Design suite. The serial radix-4 multiplier computes a 256-bit modular multiplication in 1.3µs, occupies 3.9K LUTs, and runs at 96 MHz. The parallel radix-4 multiplier takes 0.77µs, occupies 5.3K LUTs, and runs at 166 MHz. The results show that the parallel radix-4 modular multiplier provides 62% and 49% speed-up over the corresponding bit serial and bit parallel versions, respectively. Thus, these designs are suitable to accelerate modular multiplication in many cryptographic processors.Index Terms-Finite field, elliptic curve cryptography (ECC), interleaved multiplication, public key cryptography (PKC). I. INTROUCTIONModular multiplication is a tedious operation that is extensively used in a variety of public key cryptographic schemes such as RSA, elliptic curve [1], [2] (ECC). Elliptic curve based cryptographic schemes enjoy much smaller key sizes as compared to RSA, which led to better bandwidth utilization, less storage requirements and lower power consumption. To achieve 128-bit advanced encryption standard (AES) security level, finite field operations in ECC is around 256-bits. Due to its computational complexity, a dedicated hardware implementation is essential to meet timing constraints of many real time applications.For speeding up modular multiplication operation several designs have been presented. These designs can be classified into three categories: designs based on NIST recommended primes [3], designs based on interleaved multiplication algorithm [4] and designs based on Montgomery multiplication algorithm [5]. A pipelined modular multiplier design reported in [6] can support five NIST recommended primes. Its datapath is comprised of 8 pipeline stages with a latency of 80 ns for prime of sizes 192, 224, 256-bits and 200 ns for 384, 256bits. It consumes 8340 slices and 259 dedicated DSPs blocks on Virtex-6 FPGA platform, which may not fit into smaller FPGAs, but is suitable for high speed applications. Designs reported in [7], [8] also exploited special structure of NIST primes. These implementations are devoted to 224 and 256bits and are not able to provide flexibility feature, which may be desirable in many applications.

Section: Implementation and Resultsmentioning

confidence: 99%

Section: Introuctionmentioning

confidence: 99%

Section: Introuctionmentioning

confidence: 99%

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Serial and parallel interleaved modular multipliers on FPGA platform

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

Wang

Scott³

2015

Self Cite

“…In every iteration, all steps in phase B of the algorithm are executed in a single cycle, therefore, this phase is completed in ⌈ n 2 ⌉ clock cycles and overall the algorithm takes ⌈ n 2 ⌉ + 4 clock cycles to perform an n-bit modular multiplication operation. The design reported in [37] in the same bit length completes modular multiplication in 1.48 us, occupies 4630 LUTs and runs at 86 MHz clock frequency. Table III shows performance results of a 256-bit implementation of the proposed radix-4 parallel modular multiplier on Virtex-6 field programmable gate array (FPGA) platform.…”

Section: Phase Bmentioning

confidence: 99%

“…The four modular multiplication units are named as MUL 1 , MUL 2 , MUL 3 , and Mul 4 , where each MUL unit performs a modular multiplication operation in ⌈ n 2 ⌉ + 4 clock cycles, whereas A/S unit takes a single cycle to execute modular addition/subtraction operation [37]. As modular multiplication is a much more time consuming operation as compared with A/S operations, therefore it is the main reason for an integration of a single A/S unit.…”

Section: Scheduling Of Point Doubling and Point Addition On Arithmetimentioning

confidence: 99%

Low latency flexible FPGA implementation of point multiplication on elliptic curves over GF(p)

Wang

2016

Circuit Theory & Apps

Self Cite

Elliptic curve cryptography (ECC) is a branch of Public-Key cryptography that is widely accepted for secure data exchange in many resource-limited devices. This paper presents a novel hardware cryptographic processor for ECC over general prime field GF(p). It is optimized on circuit level by introducing new parallel modular multiplication algorithm with its efficient hardware architecture, which offers significant improvement over the previously used techniques. Subsequently, on the system level, it is optimized by exploiting available high degree of parallelism using projective coordinates by incorporating four parallel multiplier units. The proposed hardware is implemented on Xilinx Virtex-4 and Virtex-6 field programmable gate arrays. A 256-bit scalar multiplication is completed in 1.43 ms and 2.96 ms in a cycle count of 207.1K on Virtex-6 and Virtex-4 field programmable gate array paltforms, respectively. The Virtex-6 implementation attains a maximum frequency of 144 MHz, occupies 32.4K look-up-tables, whereas on Virtex-4 it is about 70 MHz with 35.7K slices. The results show that the proposed design offers a significant improvement in computation time with a significant reduction in cycle count as compared with the other reported designs. Therefore, it is a good choice to be used in many ECC-based schemes.FPGA, ELLIPTIC CURVE CRYPTOGRAPHY (ECC), MODULAR MULTIPLIER 215 public, while scalar d is private parameters. Mathematically, finding the value of d, while knowing the Q and P is known as elliptic curve discrete logarithm problem (ECDLP), which is the basis of mathematical security of all ECC cryptosystems. Because it is computationally hard to reverse the EC scalar multiplication operation provided that the involved parameters are chosen carefully. However, ECDLP can be bypassed by exploiting several algorithmic and implementation weaknesses termed as side channel attacks (SCA) [7]. SCA can be used to attack any physical implementation. For example, if one can have somehow access to a cryptographic device, then he may be able to reveal d by monitoring timing and power consumption profiles of the device. Simple and most common SCAs are based on timing and simple power analysis [8,9].Several hardware architectures have been developed to efficiently compute the EC scalar multiplication operation [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25]. Among these, [10,11] are based on ECs and prime fields recommended by National Institute of Standards and Technology (NIST) [26], while all other designs support any general prime field GF(p). In [27,28] listed nearly all reported EC scalar multiplier hardware architectures. Typically, NIST-based designs are superior in terms of performance, however are less flexible to design over general GF(p). All these designs developed EC scalar multiplier architecture using standard EC Weierstrass representation. ContributionThis paper presents a novel low latency flexible EC scalar multiplier architecture over GF(p). In addition to the low latency feature, the pr...

A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

Shah

Azmat

et al. 2018

Circuit Theory & Apps

SummaryThis workpresents a novel high‐speed redundant‐signed‐digit (RSD)‐based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre‐computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state‐of‐the‐art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)‐only common Z coordinate (co‐Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V‐6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed‐up over the state‐of‐the‐art.