Low latency flexible FPGA implementation of point multiplication on elliptic curves over GF(p)

Abstract

Elliptic curve cryptography (ECC) is a branch of Public-Key cryptography that is widely accepted for secure data exchange in many resource-limited devices. This paper presents a novel hardware cryptographic processor for ECC over general prime field GF(p). It is optimized on circuit level by introducing new parallel modular multiplication algorithm with its efficient hardware architecture, which offers significant improvement over the previously used techniques. Subsequently, on the system level, it is optimized by exploiting available high degree of parallelism using projective coordinates by incorporating four parallel multiplier units. The proposed hardware is implemented on Xilinx Virtex-4 and Virtex-6 field programmable gate arrays. A 256-bit scalar multiplication is completed in 1.43 ms and 2.96 ms in a cycle count of 207.1K on Virtex-6 and Virtex-4 field programmable gate array paltforms, respectively. The Virtex-6 implementation attains a maximum frequency of 144 MHz, occupies 32.4K look-up-tables, whereas on Virtex-4 it is about 70 MHz with 35.7K slices. The results show that the proposed design offers a significant improvement in computation time with a significant reduction in cycle count as compared with the other reported designs. Therefore, it is a good choice to be used in many ECC-based schemes.FPGA, ELLIPTIC CURVE CRYPTOGRAPHY (ECC), MODULAR MULTIPLIER 215 public, while scalar d is private parameters. Mathematically, finding the value of d, while knowing the Q and P is known as elliptic curve discrete logarithm problem (ECDLP), which is the basis of mathematical security of all ECC cryptosystems. Because it is computationally hard to reverse the EC scalar multiplication operation provided that the involved parameters are chosen carefully. However, ECDLP can be bypassed by exploiting several algorithmic and implementation weaknesses termed as side channel attacks (SCA) [7]. SCA can be used to attack any physical implementation. For example, if one can have somehow access to a cryptographic device, then he may be able to reveal d by monitoring timing and power consumption profiles of the device. Simple and most common SCAs are based on timing and simple power analysis [8,9].Several hardware architectures have been developed to efficiently compute the EC scalar multiplication operation [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25]. Among these, [10,11] are based on ECs and prime fields recommended by National Institute of Standards and Technology (NIST) [26], while all other designs support any general prime field GF(p). In [27,28] listed nearly all reported EC scalar multiplier hardware architectures. Typically, NIST-based designs are superior in terms of performance, however are less flexible to design over general GF(p). All these designs developed EC scalar multiplier architecture using standard EC Weierstrass representation. ContributionThis paper presents a novel low latency flexible EC scalar multiplier architecture over GF(p). In addition to the low latency feature, the pr...

An Efficient Hardware Implementation of Finite Field Inversion for Elliptic Curve Cryptography

“…The performance metrics of AT is decreased around 90% and throughput is increased around 294%. So, our design provide better results in terms of AT and throughput with respect to recent designs are Hossain et al [2], Javeed [3]- [4] and Mrabet et al [5].…”

“…So, we used throughput rate parameter and area-delay product (AT) parameter for comparison purposes. Table II, gives the simulated results and performance from various papers presented by Hossain et al [2], Liu et al [3], Lee et al [4], Vliegen [5], Ghosh et al [6], McIvor et al [7], Daly et al [8] and Kudithi et al [9]. We can observe that the results from Hossain et al [2] and Kudithi [9] are better in terms of area and computation time when compared with other literature results.…”

“…Javeed [3]- [4] designs has implemented using Virtex-6 FPGA. The throughput is improved around 68% to 75% and AT is decreased around 88% to 90% when compared with our design.…”

“…One of the efficient algorithm Binary Inversion Algorithm to compute modular inversion, which is easier to implement RTL based hardware perspective and also more area-efficient with high-speed operation. The modular inversion/division algorithm for ECC over p F was developed by Hossain [1,2], Javeed [3]- [4], Mrabet [5], Kudithi [6], Liu [7], Lee [8], Vliegen [9], Ghosh [10], McIvor [11], and Daly [12][13]. Among these McIvor described different hardware architectures for modular inversion algorithm and remaining authors are used binary inversion algorithm or extended Euclidean algorithm.…”

Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve

“…Several hardware implementations of ECC have been reported in [ 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 53 ], where some authors aimed to minimize the area use while others tried to reduce the computation time. Achieving a higher processing speed with low-area use is technically challenging.…”