SummaryElliptic curve cryptography (ECC) schemes are widely adopted for the digital signature applications due to their key sizes, hardware resources, and higher security per bit than Rivest‐Shamir‐Adleman (RSA). In this work, we proposed a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field,
. This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources, which is synthesized both in field‐programmable gate array (FPGA) and application‐specific integrated circuit (ASIC). The proposed ECSM takes 1.76 and 2.44 ms on Virtex‐7 FPGA platform over 224‐bit and 256‐bit prime field, respectively. Similarly, ASIC (GF 40 nm complementary metal‐oxide semiconductor [CMOS]) technology implementation provides energy efficient with a latency of 0.46 and 0.6 ms over prime field
and
, respectively. This design provides better area‐delay product and high throughput value in both FPGA and ASIC when compared with other designs.
The modular inversion operation is an essential hardware design for computing speed when we use it in cryptography applications. Through this work, we present a FSM based design methodology to achieve speed, area and high-performance modular binary inversion algorithm over 256-bit prime field. The proposed architecture implemented using Xilinx Virtex-7 FPGA device, it achieves 37% reduction in area-delay product and 15% and 16% of improvement in speed and throughput respectively, when compared with existing designs. Also, ASIC based implementation is done using TSMC 65nm CMOS technology, the synthesis results achieved the maximum operating clock frequency is 833 MHz and throughput of 626Mbps, which makes it suitable for speed-critical cryptoapplications.
Power consumption plays a crucial role in the design of portable wireless communication devices, as it has a direct influence on the battery weight and volume required for operation. This article presents a novel design for a linear LMS equalizer for the optimization of filter order. The article describes the use of a variable length algorithm for dynamically updating the tap-length of the LMS adaptive filter to optimize the performance and for reducing the power in the adaptive filter core. An algorithm is applied to reduce and adjust the order of the filter in linear equalizer according to the channel conditions. The proposed design is implemented in the synopsis TSMC 65nm technology. The results from using the algorithm uses 28% less power when compared with the conventional 64-tap fixed length adaptive filter design. It has also been shown that the low-complexity of the additional circuitry needed for the variable length adaptive filter presents minimal overhead for this architecture.
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