A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

Shah, Yasir; Javeed, Khalid; Azmat, Shoaib; Wang, Xiaojun

doi:10.1002/cta.2504

Cited by 24 publications

(28 citation statements)

References 46 publications

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“…On the earlier platform, Shah et al [ 17 ] proposed a redundant-signed-digit (RSD)-based ECC processor leveraging Montgomery multiplier that uses parallel computation technique operating in (X,Y)-only co-Z arithmetic. They also provide a relatively comprehensive comparative analysis with other methods, in which they evaluate their proposed method in Virtex-2 up to Virtex-6, without using any DSPs and BRAMs.…”

Section: Hardware Implementation Results and Discussionmentioning

confidence: 99%

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High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

Awaludin

Larasati

Kim

2021

Sensors

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In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes digital signal processor (DSP) primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation for 256-bit modulus size on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020 yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

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Section: Hardware Implementation Results and Discussionmentioning

confidence: 99%

“…To maintain hardware implementation flexibility, several methods in literature have proposed to accelerate ECC computation for generic curves rather than a special curve, including [ 11 , 14 , 15 , 16 , 17 , 18 , 19 , 20 ]. In 2013, Ma et al.…”

Section: Introductionmentioning

confidence: 99%

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

Awaludin

Larasati

Kim

2021

Sensors

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“…A few NIST‐based designs have been proposed for

P - 384

and

P - 521

. The modular multiplier designs in [18, 34] are flexible for all NIST primes, while those presented in [35, 36] target general prime fields. Therefore, the comparison of our specific Curve448 design with these designs may not be fair.…”

Section: Implementation Results and Comparisonmentioning

confidence: 99%

“…The NIST-based algorithms perform a sequence of multi-precision additions and subtractions as an alternative to the costly division. Many design efforts have been made to propose low latency modular multipliers for various ECs meeting different computational time and area requirements [33][34][35][36][37][38][39][40]. However, to the authors' best knowledge only a single design has been proposed for Curve448.…”

Section: Modular Multiplicationmentioning

confidence: 99%

LUT‐based high‐speed point multiplier for Goldilocks‐Curve448

Shah

Javeed

Shehzad

et al. 2020

IET Computers & Digital Techniques

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Recent studies have shown that existing elliptic curve-based cryptographic standards provide backdoors for manipulation and hence compromise the security. In this regard, two new elliptic curves known as Curve448 and Curve25519 are recently recommended by IETF for transport layer security future generations. Hence, cryptosystems built over these elliptic curves are expected to play a vital role in the near future for secure communications. A high-speed elliptic curve cryptographic processor (ECCP) for the Curve448 is proposed in this study. The area of the ECCP is optimised by performing different modular operations required for the elliptic curve Diffie-Hellman protocol through a unified architecture. The critical path delay of the proposed ECCP is optimised by adopting the redundant-signed-digit technique for arithmetic operations. The segmentation approach is introduced to reduce the required number of clock cycles for the ECCP. The proposed ECCP is developed using look-up-tables (LUTs) only, and hence it can be ported to any field-programmable gate array family or standard ASIC libraries. The authors' ECCP design offers higher speed without any significant area overhead to recent designs reported in the literature.

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“…Several custom hardware architectures for field multiplication based on MM and IM algorithms have been proposed. The designs 7,[16][17][18][19] are based on MM method and incorporated different circuit level optimization techniques such as residue number systems (RNS), redundant sign digit (RSD), carry save adders (CSAs), etc. The designs reported in Barker and Dang 7 and Özcan and Erdem 18 also targeted MM method by utilizing in-built features of modern field programmable gate array (FPGA) devices.…”

mentioning

confidence: 99%

High‐speed parallel reconfigurable F_p multipliers for elliptic curve cryptography applications

Javeed

Saeed

Gregg

2022

Circuit Theory & Apps

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Elliptic curve cryptography (ECC) protocols due to higher security strength per bit have been widely accepted and deployed. Finite field multiplication is the most computational intensive operation in data security protocols developed using ECC. This paper presents two high-speed parallel re-configurable finite field multipliers: PIMD-2 and PIMD-3 over prime field (F p ) for ECC applications. The proposed designs are based on the new novel optimized interleaved multiplication algorithms. This work first identifies room of parallelism by investigating independent operations in the standard interleaved multiplication method and subsequently proposes high-speed hardware architectures that allow the parallel execution of these operations. Due to the introduced modifications, the critical path delays and clock cycle consumption in the PIMD-2 and PIMD-3 designs are reduced simultaneously. The proposed F p multipliers are synthesized using Xilinx ISE Design Suite and implemented on Virtex-5 and Virtex-6 field programmable gate array (FPGA) platforms for common ECC key sizes 160-521 bits. The implementation results reveal that the proposed designs are highly efficient, provided up to 3Â improvement in latency with lower area-delay product and higher throughput per FPGA slice as compared to the state-of-the-art. K E Y W O R D Selliptic curve cryptography, field programmable gate array, finite field multiplication, hardware accelerators, public key cryptography | INTRODUCTIONToday data security mechanism is essential in Internet of Things (IoTs) and must be developed considering computational power and resource availability of underlying systems. RSA 1 and elliptic curve cryptography (ECC) 2,3 are two popular public key (PK) schemes widely used for providing many interesting security protocols. [4][5][6] Different standardization bodies recommend ECC over RSA for deployment in the future. Different recommendations show that ECC key sizes are 10-30 times smaller than the traditional RSA scheme. 7 This key size gap is further expected to increase as the security challenges arise due to rapid advancement in the cryptanalysis techniques.RSA is an exponential scheme, and its implementation involves repeated finite field multiplication operation. On the other hand, ECC is structured on finite field addition, subtraction, multiplication, and inversion/division primitives. However, due to computational complexity of finite field inversion/division operations, different coordinate systems have been developed to avoid these operations at the cost of extra finite field multiplications. 5,8-10 Thus, a finite field

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A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

Cited by 24 publications

References 46 publications

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

LUT‐based high‐speed point multiplier for Goldilocks‐Curve448

High‐speed parallel reconfigurable F_p multipliers for elliptic curve cryptography applications

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A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

Cited by 24 publications

References 46 publications

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

LUT‐based high‐speed point multiplier for Goldilocks‐Curve448

High‐speed parallel reconfigurable Fp multipliers for elliptic curve cryptography applications

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High‐speed parallel reconfigurable F_p multipliers for elliptic curve cryptography applications