High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

Awaludin, Asep Muhamad; Larasati, Harashta Tatimma; Kim, Howon

doi:10.3390/s21041451

Cited by 24 publications

(38 citation statements)

References 36 publications

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“…They synthesized the design on a 65 nm CMOS technology. The work in [21] is a ECC Processor for Weierstrass Curves over GF(p) implemented on 7-series FPGA. It adopts a Montgomery multiplication which is constructed employing a large number of Digital Signal Processor (DSP) primitives.…”

Section: Related Workmentioning

confidence: 99%

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Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications

et al. 2021

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Cybersecurity is a critical issue for Real-Time IoT applications since high performance and low latencies are required, along with security requirements to protect the large number of attack surfaces to which IoT devices are exposed. Elliptic Curve Cryptography (ECC) is largely adopted in an IoT context to provide security services such as key-exchange and digital signature. For Real-Time IoT applications, hardware acceleration for ECC-based algorithms can be mandatory to meet low-latency and low-power/energy requirements. In this paper, we propose a fast and configurable hardware accelerator for NIST P-256/-521 elliptic curves, developed in the context of the European Processor Initiative. The proposed architecture supports the most used cryptography schemes based on ECC such as Elliptic Curve Digital Signature Algorithm (ECDSA), Elliptic Curve Integrated Encryption Scheme (ECIES), Elliptic Curve Diffie-Hellman (ECDH) and Elliptic Curve Menezes-Qu-Vanstone (ECMQV). A modified version of Double-And-Add-Always algorithm for Point Multiplication has been proposed, which allows the execution of Point Addition and Doubling operations concurrently and implements countermeasures against power and timing attacks. A simulated approach to extract power traces has been used to assess the effectiveness of the proposed algorithm compared to classical algorithms for Point Multiplication. A constant-time version of the Shamir’s Trick has been adopted to speed-up the Double-Point Multiplication and modular inversion is executed using Fermat’s Little Theorem, reusing the internal modular multipliers. The accelerator has been verified on a Xilinx ZCU106 development board and synthesized on both 45 nm and 7 nm Standard-Cell technologies.

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Section: Related Workmentioning

confidence: 99%

“…The work in [19] is a review paper that shows some guidelines to aid hardware designers in choosing the combination of methods and algorithms for different application classes. Works like [20][21][22][23][24] focus on the acceleration of ECC.…”

Section: Introductionmentioning

confidence: 99%

Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications

et al. 2021

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“…Here, the design parameters determine the requirements under which a system is expected to operate. Therefore, some most recent throughput optimized (or high-speed) ECC implementations are reported in [14][15][16][17]. Similarly, area-improving implementations are considered in [18][19][20][21].…”

Section: State-of-the-art Pm Architecturesmentioning

confidence: 99%

“…Their architecture takes 2.50, 4.09, 5.81, 9.50, and 18.51 µs for one PM calculation on Xilinx Virtex-5 FPGA over GF2 163 , GF2 233 , GF2 283 , GF2 409 , and GF2 571 , respectively. In [16], the high speed is achieved with a combined use of the schoolbook long and Karatsuba multiplication algorithms. It allows for better parallelization while retaining low complexity.…”

Section: State-of-the-art Pm Architecturesmentioning

confidence: 99%

“…The aforementioned discussion reveals that several optimization techniques, i.e., pipelining (used in [21,22]), algorithmic parallelism (adopted in [15]), segmented modular multipliers (employed in [24]), and bit-parallel multipliers (targeted in [16,18]) have been used in existing architecture to speed up the computation of PM in ECC. The use of bit-serial and digit-serial multipliers, used in [19,20], results in a decrease in hardware resources (area) with a decrease in performance of the architecture (compared with bitparallel modular multipliers).…”

Section: State-of-the-art Pm Architecturesmentioning

confidence: 99%

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A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography

et al. 2021

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This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 μs for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 μW) and Kintex-7 (61 μW) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.

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Area‐time efficient point multiplication architecture on twisted Edwards curve over general prime field GF(p)

Javeed

El-Moursy

2023

Circuit Theory & Apps

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Elliptic curve point multiplication is the main primitive required in almost all security schemes using elliptic curve cryptography (ECC). It is the leading computationally intensive operation that sets the overall performance of the associated cryptosystem. This work presents a highly novel area–time efficient elliptic curve point multiplier over a general prime field . It is based on an efficient radix‐23 parallel multiplier, which performs a ‐bit multiplication in clock cycles. On the system level, the twisted Edwards curves with unified point addition using projective coordinates are adopted, where an efficient scheduling technique is presented to schedule several operations on deployed modular arithmetic units. Due to the introduced optimization at different stages of the design, latency, hardware resource requirement, and total clock cycle count are reduced significantly. Synthesis, and implementation of the proposed design over different Xilinx FPGA platforms are completed using the Xilinx ISE Design Suite tool for key sizes of 192, 224, and 256 bits. The 256‐bit Xilinx Virtex‐7 FPGA implementation reveals that it completes a single point multiplication operation in 0.8 ms and occupies 6.7K FPGA slices in a clock cycle count of 132.2K. It produces significantly better area–time product and throughput per slice than the contemporary designs. The proposed design also has the potential to counter simple power analysis and timing attacks. Thus, it is an elegant solution to develop ECC‐based cryptosystems for applications, where both speed and hardware resource consumption are important.

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High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

Cited by 24 publications

References 36 publications

Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications

Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications

A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography

Area‐time efficient point multiplication architecture on twisted Edwards curve over general prime field GF(p)

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