Radiation hardened 2Mbit SRAM in 180nm CMOS technology

Arbat, A.; Calligaro, Cristiano; Roizin, Yakov; Nahmad, D.

doi:10.1109/estel.2012.6400164

Cited by 11 publications

(5 citation statements)

References 14 publications

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“…In this case, many contributions can be distinguished, but the main ones are the latch-up of the circuits and the single event effects (SEE). Some of these effects can be avoided by properly designing the circuits using radiation hardening-by-design techniques [8] - [9]. This is not the case for DDD effects related to the damaging of the crystalline structure of the substrate.…”

Section: Radiation Effects On Cmos and S-flash Cellmentioning

confidence: 97%

“…The used RHBD approach is divided into three levels -architectural, schematic and layout-addressing different solutions to radiation effects. From the point of view of the memory periphery a RHBD approach has been considered as in the previous works related to rad-hard SRAM memories [9]. From the point of view of the S-Flash cell, a similar approach has been considered to enhance the radiation hardness of the design.…”

Section: Memory Architecture Radiation Enhancementmentioning

confidence: 99%

See 1 more Smart Citation

SkyFlash EC project: Architecture for a 1Mbit S-Flash for space applications

Arbat

Calligaro

Dayan

et al. 2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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This work presents an innovative architecture to fabricate a non volatile memory for space applications using a SFlash memory cell. The design takes into account the different effects of the radiation that could damage the circuits and the memory cell in harsh environments. The memory cell has been developed by TowerJazz Semiconductors to be compatible with the standard 180nm CMOS process. A 1Mbit prototype has been designed using the presented architecture.

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Section: Radiation Effects On Cmos and S-flash Cellmentioning

confidence: 97%

Section: Memory Architecture Radiation Enhancementmentioning

confidence: 99%

SkyFlash EC project: Architecture for a 1Mbit S-Flash for space applications

Arbat

Calligaro

Dayan

et al. 2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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“…2). This arrange ment is suit able, for ex am ple, for test ing the rad-hard mem o ries [11][12][13].…”

Section: The Test Meth Od Ol Ogy De Vel Op Mentmentioning

confidence: 99%

The methodology for active testing of electronic devices under the radiations

et al. 2018

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The meth od ol ogy, de vel oped for ac tive test ing of elec tronic de vices un der the ra di a tions, is pre sented. The test set-up in cludes a gamma-ray fa cil ity, the hard ware board/fix tures and the soft ware tools pur posely de signed and re al ized. The meth od ol ogy is so wide-rang ing to al low us the ver i fi ca tion of dif fer ent classes of elec tronic de vices, even if only ap pli ca tion ex am ples for static ran dom ac cess mem ory mod ules are re ported.Key words: test ing methodology, elec tronic de vice, to tal ion iz ing dose, sin gle event ef fect, gamma ray A. Parlato, et al.: The Meth od ol ogy for Ac tive Test ing of Elec tronic De vices .

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“…Since, the chip is divided into blocks the case is reduced to single bit being affected. And the affected byte is recovered using ECC [44].The schematic level hardening is achieved by decreasing the number of floating gates, restricting the pass transistor and increasing the parasitic capacitance. At layout level edgeless transistors are used to avoid thick oxides.…”

Section: Cmos Srammentioning

confidence: 99%

Single Event Upset Detection and Hardening schemes for CNTFET SRAM – A Review

Rajalakshmi¹,

Sudhakar²

2015

JESTR

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Carbon nanotubes (CNT) provide a better alternative of silicon, when it comes to nano scales. Thanks to its high stability and high performance of carbon nanotube, CNT based FET (CNTFET) devices which are gaining popularity of late. Single Event Upset (SEU) in a device is caused due to radiation. Radiation can be through two ways, one due to charge particles present in the atmosphere and other due to alpha particles. In this article we review some of the detection and hardening schemes in CMOS SRAM and make related simulations on CNTFET SRAM. The aim of this paper is to present the challenges the CNTFET SRAM is facing when the radiation effects are introduced. A full experimentation of all the schemes of detection and correction schemes will be beyond the scope, so only certain experiments that can be well carried out with CNTFET SRAM memory is more focussed.

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Radiation hardened 2Mbit SRAM in 180nm CMOS technology

Cited by 11 publications

References 14 publications

SkyFlash EC project: Architecture for a 1Mbit S-Flash for space applications

SkyFlash EC project: Architecture for a 1Mbit S-Flash for space applications

The methodology for active testing of electronic devices under the radiations

Single Event Upset Detection and Hardening schemes for CNTFET SRAM – A Review

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