Radiation hard DMAPS pixel sensors in 150 nm CMOS technology for operation at LHC

Barbero, M.; Barrillon, P.; Bespin, C.; Bhat, S.; Breugnon, P.; Caicedo, I.; Chen, Z.; Değerli, Y.; Dingfelder, J.; Godiot, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Huegging, F.; Krüger, H.; Moustakas, Konstantinos; Ouraou, A.; Pangaud, P.; Perić, I.; Pohl, D.; Rymaszewski, P.; Schwemling, Philippe; Vandenbroucke, M.; Wang, T.; Wermes, N.

doi:10.1088/1748-0221/15/05/p05013

Cited by 20 publications

(17 citation statements)

References 37 publications

(43 reference statements)

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“…The leakage current, however, reaches the μA order before -20 V of bias voltage. This result is unexpected and extremely higher than the usual nA values before the breakdown voltage [4]. Further investigation revealed that the high leakage current is due to the lack of guard ring structures enclosing the ASIC and other issues that will be discussed in detail in the next section.…”

Section: Pos(vertex2019)019mentioning

confidence: 84%

“…The pixels, which have a size of 50 μm x 50 μm, integrate all the analogue and digital readout electronics for column drain readout in their sensing areas. This represents a considerable improvement in comparison to another state-of-the-art depleted CMOS detector prototype in the same technology node, where a pixel size of 50 μm x 250 μm was achieved with similar readout electronics also integrated in the sensing area of the pixel [4]. However, the smaller pixel size of RD50-MPW1 is only possible after sacrificing some features.…”

Section: Design Of Rd50-mpw1mentioning

confidence: 95%

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Recent depleted CMOS developments within the CERN-RD50 framework

Figueras¹

2020

Proceedings of the 28th International Workshop on Vertex Detectors — PoS(Vertex2019)

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Depleted CMOS sensors are groundbreaking position sensitive detectors that offer a competitive and cost-effective solution for a large range of particle tracking applications. In spite of their substantial advantages, these sensors require further research to become even more performant and meet the ever more demanding requirements of particle physics experiments planned for the near future. In this context, the CERN-RD50 collaboration has started a new R&D programme to study and develop depleted CMOS sensors as one of its main priorities. This article presents the depleted CMOS R&D programme within the CERN-RD50 collaboration. It describes the design aspects of the two prototype ASICs developed so far, which are in a 150 nm High Voltage-CMOS (HV-CMOS) process and manufactured on high resistivity substrates. The first prototype ASIC, named RD50-MPW1 and delivered after fabrication in April 2018, integrates a matrix of 50 μm x 50 μm pixels with all the analogue and digital readout electronics for column drain readout embedded in their sensing areas. The second prototype ASIC, named RD50-MPW2 and delivered after fabrication in January 2020, integrates a matrix of 60 μm x 60 μm pixels with analogue readout electronics to reduce the sensor response time. RD50-MPW2 incorporates new methods to optimise the leakage current of the sensor. The article discusses laboratory measurements of the performance evaluation of RD50-MPW1, while those of RD50-MPW2 will be published elsewhere.

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Section: Pos(vertex2019)019mentioning

confidence: 84%

Section: Design Of Rd50-mpw1mentioning

confidence: 95%

Recent depleted CMOS developments within the CERN-RD50 framework

Figueras¹

2020

Proceedings of the 28th International Workshop on Vertex Detectors — PoS(Vertex2019)

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“…The chip is produced on 10 Ω•cm, 200 -500 Ω•cm, 1.9 kΩ•cm, and 3 kΩ•cm substrate resistivity wafers. This prototype includes test structures (marked as 1 and 6 in the figure), an 8 × 8 pixel matrix (2), an analog buffer (3), a Single Event Upset (SEU) tolerant memory array (4) and a bandgap voltage reference (5). Compared with the previous version RD50-MPW1, this chip reduces the leakage current by preventing certain filling layers added by the foundry and adding a series of guard rings [7].…”

Section: Rd50-mpw2mentioning

confidence: 99%

“…However, their slow charge collection by diffusion and low radiation tolerance (10 13 1 MeV neq/cm 2 ) [3] limit the application of CMOS sensors to low rate and low radiation experiments only, such as the ALICE Inner Tracker System (ITS) Upgrade. To achieve monolithic sensors with advanced performance, High Voltage CMOS (HV-CMOS) sensors [4] are being developed for faster charge collection by drift and higher radiation tolerance (10 15 1 MeV neq/cm 2 ) [5]. The Mu3e experiment at the Paul Scherrer Institute (PSI) in Switzerland has adopted monolithic HV-CMOS sensors for its pixel tracker [6] and other experiments, such as the LHCb Upgrade Ib and II and CLIC, are considering this sensor technology as well.…”

Section: Introductionmentioning

confidence: 99%

Development of RD50-MPW2: a high-speed monolithic HV-CMOS prototype chip within the CERN-RD50 collaboration

Zhang¹,

Casse²,

Massari³

et al. 2020

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2019)

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“…With emerging CMOS technology, electronics can be integrated onto the silicon sensor material, which enables the pixel pitch to be reduced drastically. [7][8][9] When a photon interacts in a semiconductor detector, electrons and holes are released and initially form a charge cloud. The size of the initial charge cloud increases with the amount of deposited energy.…”

Section: Introductionmentioning

confidence: 99%

1-μm spatial resolution in silicon photon-counting CT detectors

et al. 2021

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. Purpose: Spatial resolution for current scintillator-based computed tomography (CT) detectors is limited by the pixel size of about 1 mm. Direct conversion photon-counting detector prototypes with silicon- or cadmium-based detector materials have lately demonstrated spatial resolution equivalent to about 0.3 mm. We propose a development of the deep silicon photon-counting detector which will enable a resolution of , a substantial improvement compared to the state of the art. Approach: With the deep silicon sensor, it is possible to integrate CMOS electronics and reduce the pixel size at the same time as significant on-sensor data processing capability is introduced. A Gaussian curve can then be fitted to the charge cloud created in each interaction.We evaluate the feasibility of measuring the charge cloud shape of Compton interactions for deep silicon to increase the spatial resolution. By combining a Monte Carlo photon simulation with a charge transport model, we study the charge cloud distributions and induced currents as functions of the interaction position. For a simulated deep silicon detector with a pixel size of , we present a method for estimating the interaction position. Results: Using estimations for electronic noise and a lowest threshold of 0.88 keV, we obtain a spatial resolution equivalent to in the direction parallel to the silicon wafer and in the direction orthogonal to the wafer. Conclusions: We have presented a simulation study of a deep silicon detector with a pixel size of and a method to estimate the x-ray interaction position with ultra-high resolution. Higher spatial resolution can in general be important to detect smaller details in the image. The very high spatial resolution in one dimension could be a path to a practical implementation of phase contrast imaging in CT.

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Radiation hard DMAPS pixel sensors in 150 nm CMOS technology for operation at LHC

Cited by 20 publications

References 37 publications

Recent depleted CMOS developments within the CERN-RD50 framework

Recent depleted CMOS developments within the CERN-RD50 framework

Development of RD50-MPW2: a high-speed monolithic HV-CMOS prototype chip within the CERN-RD50 collaboration

1-μm spatial resolution in silicon photon-counting CT detectors

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