Recent depleted CMOS developments within the CERN-RD50 framework

Abstract

Depleted CMOS sensors are groundbreaking position sensitive detectors that offer a competitive and cost-effective solution for a large range of particle tracking applications. In spite of their substantial advantages, these sensors require further research to become even more performant and meet the ever more demanding requirements of particle physics experiments planned for the near future. In this context, the CERN-RD50 collaboration has started a new R&D programme to study and develop depleted CMOS sensors as one of its main priorities. This article presents the depleted CMOS R&D programme within the CERN-RD50 collaboration. It describes the design aspects of the two prototype ASICs developed so far, which are in a 150 nm High Voltage-CMOS (HV-CMOS) process and manufactured on high resistivity substrates. The first prototype ASIC, named RD50-MPW1 and delivered after fabrication in April 2018, integrates a matrix of 50 μm x 50 μm pixels with all the analogue and digital readout electronics for column drain readout embedded in their sensing areas. The second prototype ASIC, named RD50-MPW2 and delivered after fabrication in January 2020, integrates a matrix of 60 μm x 60 μm pixels with analogue readout electronics to reduce the sensor response time. RD50-MPW2 incorporates new methods to optimise the leakage current of the sensor. The article discusses laboratory measurements of the performance evaluation of RD50-MPW1, while those of RD50-MPW2 will be published elsewhere.

Study of neutron irradiation effects in Depleted CMOS detector structures

“…As the name suggests, RD50-MPW1 was the first chip designed by the RD50 collaboration and details about its functionalities and performance can be found in [7]. Due to imperfections in the design of the RD50-MPW1 chip, pixel current was higher than expected and already started to rise rapidly above a reverse bias voltage of ∼ 30 V. This initiated the submission of RD50-MPW2 [8] with the shortcomings corrected so taht the pixels could be biased with over 110 V.…”

RD50-MPW3: a fully monolithic digital CMOS sensor for future tracking detectors

“…In one of RD50-MPW3's predecessors RD50-MPW1, crosstalk noise was detected between signal lines that are routed with the minimum spacing allowed by the design rule [1]. To alleviate routing congestion and minimise coupling between metal lines, the pixel matrix of RD50-MPW3 is designed using the double-column architecture, where 64 pixel columns are organised into 32 double columns (128 pixels in each double column).…”

“…The digital readout electronics implements improvements on that used in RD50-MPW1 [1]. It adds a logic to prevent noisy pixels from writing data bus by enabling the signal MASK as seen in figure 3.…”

“…To further improve and demonstrate the performance of Depleted Monolithic Active Pixel Sensors (DMAPS), the CERN-RD50 CMOS group has designed a series of prototype chips using the 150 nm HV-CMOS process from LFoundry S.r.l. Following the first two designs, RD50-MPW1 and RD50-MPW2 [1,2], a further chip called RD50-MPW3 has been developed. The development of these sensors targets high granularity for precise tracking and tolerance to harsh radiation environments (1 × 10 15 n eq /cm 2 and 1 MGy) in future experiments.…”

Overview of CMOS Sensors for Future Tracking Detectors

“…A second device, the RD50-MPW2 [30], was designed to test new design approaches to minimize the leakage current by preventing certain filling layers added by the foundry and adding a series of guard rings [31]. A new pixel readout electronics design was also implemented to improve the speed of the readout electronics [32,33]. This is a smaller device, with a size of about 3 mm by 2 mm and a thickness of 280 µm.…”