Radiation effects and radiation hardness solutions for single-walled carbon nanotube-based thin film transistors and logic devices

Zhao, Yudan; Li, Dongqi; Lin, Xingyi; Liu, Junku; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shanhui; Li, Qunqing

doi:10.1016/j.carbon.2016.07.033

Cited by 22 publications

(25 citation statements)

References 41 publications

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“…Similar results were obtained in another study for p-type SWCNT network TFTs irradiated in air [72], and furthermore revealed improved junction contact performance after irradiation. The density of the CNTs on the film also plays an important factor as higher density CNTs contribute to reduced adsorption mechanisms.…”

Section: Thin Film 2-d Material and Nanotube Transistorssupporting

confidence: 90%

“…Donors created in this insulating layer from the irradiation caused negative V th , but for network-type CNTs. The insulating layer also reduced the effect of irradiation, and therefore Zhao et al [72] proposed covering the p-type devices with insulating layers that do not switch the polarity of the device, decreasing the thickness of the insulating layers to reduce the number of fixed charges introduced by them, and irradiating the device during fabrication to make the junctions saturated. Further to this, they exhibited TID-hardened logic inverters based on ambipolar TFTs by covering the p-type TFTs with Al 2 O 3 .…”

Section: Thin Film 2-d Material and Nanotube Transistorsmentioning

confidence: 99%

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Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Chatzikyriakou

Morgan

Groot

2018

IEEE Trans. Electron Devices

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-From man-made satellites and interplanetary missions to fusion power plants, electronic equipment that needs to withstand various forms of irradiation is an essential part of their operation. Examination of total ionizing dose (TID) effects in electronic equipment can provide a thorough means to predict their reliability in conditions where ionizing dose becomes a serious hazard. In this paper, we provide a historical overview of logic and memory technologies that made the biggest impact both in terms of their competitive characteristics and their intrinsically hardened nature against TID. Further to this, we also provide guidelines for hardened device designs and present the cases where hardened alternatives have been implemented and tested in the lab. The technologies that we examine range from silicon-on-insulator and FinFET to 2-D semiconductor transistors and resistive random access memory.Index Terms-2-D semiconductor, carbon, CMOS, deep submicrometer, FinFET, graphene, MoS2, resistive random access memory (RRAM), silicon-on-insulator (SOI), thin film, total ionizing dose (TID), ultrathin buried oxide (UTBOX).

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Section: Thin Film 2-d Material and Nanotube Transistorssupporting

confidence: 90%

Section: Thin Film 2-d Material and Nanotube Transistorsmentioning

confidence: 99%

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Chatzikyriakou

Morgan

Groot

2018

IEEE Trans. Electron Devices

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“…A single‐walled CNT (SWCNT) possesses cross‐linked, strong CC bonds at the nanometer scale and low atomic numbers and is an especially attractive material for building radiation‐hard FETs . Furthermore, additional advantages in the device structure of CNT film FETs reinforce the radiation hardness.…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, additional advantages in the device structure of CNT film FETs reinforce the radiation hardness. For example, a multichannel structure is beneficial for the resistance of single event effects (SEEs), and radiation‐induced charge accumulation in isolation regions is completely avoided in CNT ICs because they do not require an isolation region . Many previous reports have studied the total ionizing dose (TID) property of CNT‐based FETs by using various radiation sources including ions, gamma radiation, protons, and electrons .…”

Section: Introductionmentioning

confidence: 99%

“…Many previous reports have studied the total ionizing dose (TID) property of CNT‐based FETs by using various radiation sources including ions, gamma radiation, protons, and electrons . Very recently, the radiation‐resistant properties of complementary CNT FETs and inverters have been explored by two different groups . However, there are still obvious deficiencies in the previous studies.…”

Section: Introductionmentioning

confidence: 99%

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High‐Performance and Radiation‐Hard Carbon Nanotube Complementary Static Random‐Access Memory

Zhu

Zhang

Peng

2019

Adv Elect Materials

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development of solution-derived CNT films with high semiconducting purity and high quality. [5][6][7][8][9][10][11][12] In particular, highperformance complementary metal-oxidesemiconductor (CMOS) FETs have been realized on CNT films through dopingfree technology. [10] Researchers have also demonstrated various kinds of ICs based on solution-derived CNT films, including fundamental logic and arithmetic gates, ring oscillators and even medium-scale ICs, [9][10][11] which shows the development potential of CNT film ICs in digital applications. However, the vast majority of ICs realized on CNT films are arithmetic/ logic units, and few works have addressed static random access memory (SRAM), which is an indispensable part of actual digital ICs. As the fastest and most expensive memory, SRAM arrays typically act as caches in the central processing unit (CPU) and should be a necessary component for constructing high-performance CNT-based CPUs or microcontroller units (MCUs) and other complete digital systems. Hersam and coworkers demonstrated a six-transistor (6-T) CMOS SRAM cell based on a CNT film for the first time. [12] However, the reported SRAMs were built based on bottom-gated CNT FETs, and measurements of the dynamic characteristics were absent. Furthermore, at the present stage, none of the CNT-based ICs, including SRAM, showed any actual advantage over conventional ICs, regardless of speed, power dissipation, or integrated density. Therefore, it is still an important issue to explore and demonstrate the potential advantages of CNT-based ICs.A single-walled CNT (SWCNT) possesses cross-linked, strong CC bonds at the nanometer scale and low atomic numbers and is an especially attractive material for building radiationhard FETs. [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28] Furthermore, additional advantages in the device structure of CNT film FETs reinforce the radiation hardness. For example, a multichannel structure is beneficial for the resistance of single event effects (SEEs), and radiation-induced charge accumulation in isolation regions is completely avoided in CNT ICs because they do not require an isolation region. [24][25][26][27] Many previous reports have studied the total ionizing dose (TID) property of CNT-based FETs by using various radiation sources including ions, gamma radiation, protons, and electrons. [23,24] Very recently, the radiation-resistant properties of complementary CNT FETs and inverters have been explored by two different groups. [26,27] However, there are still obvious deficiencies in the Significant progress on carbon-nanotube (CNT) electronics means that they are a serious candidate for use in high-performance integrated circuits (ICs). However, few works have focused on fabricating and exploring CNT complementary metal-oxide-semiconductor (CMOS) static random-access memory (SRAM), which is an integral part of most digital ICs. High-performance complementary top-gated field-effect transistors (FETs) are fabricated through a doping-free technology based on so...

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Inverse Hysteresis and Ultrasmall Hysteresis Thin‐Film Transistors Fabricated Using Sputtered Dielectrics

Zhao

Huo

Xiao

et al. 2017

Adv Elect Materials

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Large current hysteresis is observed in carbon nanotube (CNT) transistors and usually shows as a positive threshold voltage shift when the gate sweeping direction changes from positive to negative. This paper reports fabrication of inverse hysteresis CNT thin‐film transistors (TFTs) using magnetron sputtered oxide as a dielectric. Stacking of the sputtered dielectric with dielectrics deposited by other methods, such as atomic layer deposition, can effectively reduce or even eliminate the hysteresis. This can be explained as a combination of the effects of surface and interface trapped charges. Additionally, this hysteresis reduction method is widely compatible with various CNT‐TFT structures and types and is even suitable for MoS2 TFTs. The output characteristics and frequency responses of large and small hysteresis devices are compared and show that the small‐hysteresis inverter has lower distortion, and that its maximum operating frequency is nearly five times larger than that of TFTs with normal hysteresis.

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Radiation effects and radiation hardness solutions for single-walled carbon nanotube-based thin film transistors and logic devices

Cited by 22 publications

References 41 publications

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

High‐Performance and Radiation‐Hard Carbon Nanotube Complementary Static Random‐Access Memory

Inverse Hysteresis and Ultrasmall Hysteresis Thin‐Film Transistors Fabricated Using Sputtered Dielectrics

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