Quantitative analysis of floating point arithmetic on FPGA based custom computing machines

Shirazi, N.; Walters, A.; Athanas, Peter

doi:10.1109/fpga.1995.477421

Cited by 116 publications

(55 citation statements)

References 4 publications

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“…FP division algorithm [6,7,9] Floating point division involves the following steps: 6. Round the above result to the allowed number (24 bits) of mantissa bits.…”

Section: Check Resultant Exponent For Overflow/underflowmentioning

confidence: 99%

Implementation of Floating Point and Logarithmic Number System Arithmetic Unit and Their Comparison for Fpga

Kumar¹,

A.K²,

Dasgupta³

2008

Int. Jour. Intel. Elec. Sys.

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Key words:Floating point (FP) representation is commonly used to represent real numbers. Some papers have suggested the use of logarithmic number system (LNS) in addition to floating point. In LNS, a real number is represented as a fixed point logarithm. Therefore multiplication and division in LNS are much simpler in comparison to that in FP, so the LNS can be beneficial if addition and subtraction can be performed with speed and accuracy equal to FP. LNS addition and subtraction requires interpolation technique for which some vales are stored in read only memory (ROM). In this paper, different sizes of ROM are used for addition and subtraction and their performances are compared to the floating point.FPGA, Logarithmic Number Systems, ROM.

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“…FP division algorithm [6,7,9] Floating point division involves the following steps: 6. Round the above result to the allowed number (24 bits) of mantissa bits.…”

Section: Check Resultant Exponent For Overflow/underflowmentioning

confidence: 99%

Implementation of Floating Point and Logarithmic Number System Arithmetic Unit and Their Comparison for Fpga

Kumar¹,

A.K²,

Dasgupta³

2008

Int. Jour. Intel. Elec. Sys.

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“…Much work in the past has been done on designing floating-point units on FPGAs [9]. Some of the work has concentrated on optimizing the large bitwidth fixed-point adder/multipliers, shifters, priority encoders etc.…”

Section: Related Workmentioning

confidence: 99%

Analysis of high-performance floating-point arithmetic on FPGAs

Govindu

Zhuo

Choi

et al.

18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.

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“…To implement the division unit, a lookup table approach is used. This technique is faster and uses less energy compared with other division algorithms [11]. To calculate a/b, we first obtain 1/b via a lookup table and perform the multiplication a×(1/b).…”

Section: Optimizations For Time and Energy Efficiencymentioning

confidence: 99%

Time and Energy Efficient Matrix Factorization Using FPGAs

Choi

Prasanna

2003

Field Programmable Logic and Application

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Abstract. In this paper, new algorithms and architectures for matrix factorization are presented. Two fully-parallel and block-based designs for LU decomposition on configurable devices are proposed. A linear array architecture is employed to minimize the usage of long interconnects, leading to lower energy dissipation. The designs are made scalable by using a fixed I/O bandwidth independent of the problem size. High level models for energy profiling are built and the energy performance of many possible designs is predicted. Through the analysis of design tradeoffs, the block size that minimizes the total energy dissipation is identified. A set of candidate designs was implemented on the Xilinx Virtex-II to verify the estimates. Also, the performance of our designs is compared with that of state-of-the-art DSP based designs and with the performance of designs obtained using a state-of-the-art commercial compilation tool such as Celoxica DK1. Our designs on the FPGAs are significantly more time and energy efficient in both cases.

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Quantitative analysis of floating point arithmetic on FPGA based custom computing machines

Cited by 116 publications

References 4 publications

Implementation of Floating Point and Logarithmic Number System Arithmetic Unit and Their Comparison for Fpga

Implementation of Floating Point and Logarithmic Number System Arithmetic Unit and Their Comparison for Fpga

Analysis of high-performance floating-point arithmetic on FPGAs

Time and Energy Efficient Matrix Factorization Using FPGAs

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