Time and Energy Efficient Matrix Factorization Using FPGAs

Abstract

Abstract. In this paper, new algorithms and architectures for matrix factorization are presented. Two fully-parallel and block-based designs for LU decomposition on configurable devices are proposed. A linear array architecture is employed to minimize the usage of long interconnects, leading to lower energy dissipation. The designs are made scalable by using a fixed I/O bandwidth independent of the problem size. High level models for energy profiling are built and the energy performance of many possible designs is predicted. Through the analysis of design tradeoffs, the block size that minimizes the total energy dissipation is identified. A set of candidate designs was implemented on the Xilinx Virtex-II to verify the estimates. Also, the performance of our designs is compared with that of state-of-the-art DSP based designs and with the performance of designs obtained using a state-of-the-art commercial compilation tool such as Celoxica DK1. Our designs on the FPGAs are significantly more time and energy efficient in both cases.

High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware

“…Some considered fixedpoint arithmetic only [28], [29], [30]. Due to the implementation complexity of the floating-point units, the work of these researchers is not suitable for floating-point-based operations.…”

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

“…It is well known that increasing this data locality has a direct relationship to the power consumed [5 -7]. Indeed, previous work has involved investigating locality properties for FPGA-based systolic array implementations [8] and an FFT-based digital receiver solution based on a Xilinx Virtex-II FPGA implementation [9]; however, the real challenge is how to influence data locality at the algorithmic level in a systematic fashion, particularly for fast transforms that may not necessarily exhibit this locality in the first instance.…”

A high-performance and energy-efficient architecture for floating-point based LUdecomposition on FPGAs

“…al. [4] and our LU architecture shown in Figure 1. Choi's block LU decomposition architecture also utilizes a matrix multiplication and subtraction architecture.…”

“…Many systolic array algorithms have been described in literature [6], [2], [4] and [7]. Rajopadhye [7] presents systolic arrays for LU decomposition.…”

“…al. [4] also use a linear array architecture. In their architecture, reciprocation and then multiplication is done instead of division.…”