Analysis of high-performance floating-point arithmetic on FPGAs

Govindu, Gokul; Zhuo, Ling; Choi, Seonil; Prasanna, Viktor K.

doi:10.1109/ipdps.2004.1303135

Cited by 98 publications

(74 citation statements)

References 2 publications

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“…Hosting such applications with high precision requirements on FPGAs is an active research area e.g. [15]. Nevertheless, integer based arithmetic requires significantly less area to implement and run significantly faster than IEEE formats [13], and some FPGA-targeting compilers do not support floating point operations.…”

Section: Computational Transformationmentioning

confidence: 99%

Profile Guided Dataflow Transformation for FPGAs and CPUs

Stewart

Bhowmik

Wallace

et al. 2015

J Sign Process Syst

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This paper proposes a new high-level approach for optimising field programmable gate array (FPGA) designs. FPGA designs are commonly implemented in low-level hardware description languages (HDLs), which lack the abstractions necessary for identifying opportunities for significant performance improvements. Using a computer vision case study, we show that modelling computation with dataflow abstractions enables substantial restructuring of FPGA designs before lowering to the HDL level, and also improve CPU performance. Using the CPU transformations, runtime is reduced by 43%. Using the FPGA transformations, clock frequency is increased from 67MHz to 110MHz. Our results outperform commercial low-level HDL optimisations, showcasing dataflow program abstraction as an amenable computation model for highly effective FPGA optimisation.

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Section: Computational Transformationmentioning

confidence: 99%

Profile Guided Dataflow Transformation for FPGAs and CPUs

Stewart

Bhowmik

Wallace

et al. 2015

J Sign Process Syst

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show abstract

“…An example of the simplest double-precision FPU from the Tensilica design library requires on the order of 150,000 gates [36]. Even though FPU units support multiplication as well as addition, and therefore would be partially unused in a distributed summation, floating point multiplication is less complicated to implement than addition [37]. Verification is non-trivial for even a circuit of this size and complexity, and this implementation is among the simplest available.…”

Section: B Applicability To Network Operationsmentioning

confidence: 99%

Extending Summation Precision for Network Reduction Operations

Bailey

Shalf

2013

2013 25th International Symposium on Computer Architecture and High Performance Computing

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Abstract-Double precision summation is at the core of numerous important algorithms such as Newton-Krylov methods and other operations involving inner products, but the effectiveness of summation is limited by the accumulation of rounding errors, which are an increasing problem with the scaling of modern HPC systems and data sets. To reduce the impact of precision loss, researchers have proposed increasedand arbitrary-precision libraries that provide reproducible error or even bounded error accumulation for large sums, but do not guarantee an exact result. Such libraries can also increase computation time significantly. We propose big integer (BigInt) expansions of double precision variables that enable arbitrarily large summations without error and provide exact and reproducible results. This is feasible with performance comparable to that of double-precision floating point summation, by the inclusion of simple and inexpensive logic into modern NICs to accelerate performance on large-scale systems.

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“…Moreover, multiple tradeoffs between latency and area can be exploited which has already been extensively studied for floating point formats [7,17,21]. There exist also parameterized IP cores which offer particularly efficient implementations for a given architecture.…”

Section: Floating Point Numbers On Fpgasmentioning

confidence: 99%

Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components

Strzodka¹,

Göddeke

2006

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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FPGAs are becoming more and more attractive for high precision scientific computations. One of the main problems in efficient resource utilization is the quadratically growing resource usage of multipliers depending on the operand size. Many research efforts have been devoted to the optimization of individual arithmetic and linear algebra operations. In this paper we take a higher level approach and seek to reduce the intermediate computational precision on the algorithmic level by optimizing the accuracy towards the final result of an algorithm. In our case this is the accurate solution of partial differential equations (PDEs). Using the Poisson Problem as a typical PDE example we show that most intermediate operations can be computed with floats or even smaller formats and only very few operations (e.g. 1%) must be performed in double precision to obtain the same accuracy as a full double precision solver. Thus the FPGA can be configured with many parallel float rather than few resource hungry double operations. To achieve this, we adapt the general concept of mixed precision iterative refinement methods to FPGAs and develop a fully pipelined version of the Conjugate Gradient solver. We combine this solver with different iterative refinement schemes and precision combinations to obtain resource efficient mappings of the pipelined algorithm core onto the FPGA.

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Analysis of high-performance floating-point arithmetic on FPGAs

Abstract: Abstract

Cited by 98 publications

References 2 publications

Profile Guided Dataflow Transformation for FPGAs and CPUs

Profile Guided Dataflow Transformation for FPGAs and CPUs

Extending Summation Precision for Network Reduction Operations

Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components

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