PVD Cu Reflow Seed Process Optimization for Defect Reduction in Nanoscale Cu/Low-k Dual Damascene Interconnects

Abstract

A novel Cu reflow seed process which utilizes physical vapor deposition (PVD) technology components has been demonstrated for nanoscale dual damascene interconnects. Prior to Cu electroplating, small features can be partially filled with Cu by this newly developed Cu reflow seed process. It is confirmed that both suitable seed coverage and appropriate reflow temperature are required for achieving ideal reflow property. Bias conditions during Cu PVD dominate seed coverage in features, and processes at moderate bias are demonstrated to provide optimum bottom and sidewall coverage, while limiting field coverage. Overall Cu fill performance was enhanced significantly and more than a 60% improvement in via-chain yield is obtained by Cu reflow seed compared to conventional seed. Furthermore, Cu lines with fewer voids and less impurities are fabricated by repeating this Cu reflow seed process several times to obtain complete feature fill, which results in lower leakage current between lines. This Cu reflow seed process is a promising candidate for improving Cu fill performance for nanoscale Cu/low-k interconnects of 32 nm critical dimension and beyond.

What can we do about barrier layer scaling to 5 nm node technology ?

“…However, smaller trenches and vias in the future node cannot be successfully filled with the conventional methods. Reflow process may be used instead [15]. Figure 2 shows the result of dynamic reflow in which Cu-Mn alloy was deposited on a SiO 2 substrate heated at 350 o C [16].…”

Study of Cu-growth feature by selective low-pressure chemical vapor deposition using a CuI precursor

“…6,7) Additionally, Cu-filling is usually performed by electroplating or electro-less plating, [8][9][10][11] using post-annealing, which allows control of the Cu grain size and increases the conductivity, thereby avoiding void-formation. 12,13) Controlling the Cu grain size, in particular, is critical for preventing an increase in Cu resistivity in nanoscale electrodes, 14) wherein an increase in the grain size often limits electron-scattering at the grain boundaries. Therefore, in terms of grain size control with conformational deposition, CVD has a significant advantage.…”

A Survey of Carbon Nanotube Interconnects for Energy Efficient Integrated Circuits

“…Thinner barrier and adhesion layers, doping of metals to enhance the grain boundary conductance, and selective capping are some of the adopted solutions improving copper interconnects. Other short-term solutions to address the scaling challenges faced by Cu include load-aware redundant double vias to avoid EM issues [6], via prefill with alternate materials (like Cobalt) with higher current migration resistance and better fill [7], ultra-thin self-forming barriers (metal oxide barriers like MnO x ) to optimize the utilizable cross-section for Cu, alternative materials for better EM [8], reflow seed layers for defect reduction [9], etc. Nevertheless, these short-term steps aim to solve one or few of the Cu-foreseen issues at once and to combine them might prove to be impractical or just economically unfeasible.…”