Pulsed-Latch Circuits: A New Dimension in ASIC Design

Kim

IEEE Trans. Circuits Syst. I

2015

Self Cite

Aggressive reduction of timing margins, called timing speculation, is an effective way of reducing the supply voltage for a pipeline circuit and thereby its power consumption. However, probability of timing error increases with the voltage scaling and hence, the errors must be corrected with small cycle penalty. We introduce an improved Razor flip-flop which makes more effective use of its shadow latch, so that a pipeline stage can correct an error while continuing to receive data. This avoids the need for repeated clock gating when timing errors happen simultaneously at different stages, or when an error persists. The new flip-flop also facilitates time-borrowing. Our technique uses less energy than the state-of-the art technique, and the energy saving increases with pipeline length: with 10 stages, 4-9% smaller energy is used.

Section: A Related Workmentioning

confidence: 99%

Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation

Kim

IEEE Trans. Circuits Syst. I

2015

Self Cite

2014 19th IEEE European Test Symposium (ETS)

“…A second multiplexer is added in the feedback path of the circuit, which is controlled by the scan enable signal SE. Furthermore, the Shadow Latch has been replaced by a Pulsed Shadow Latch (PSL) which is synchronized by a pulsed clock signal PCLK [4]. The rising edge of the PCLK signal is delayed with respect to the corresponding edge of the CLK signal, as it is required by the Razor technique.…”

Section: The Proposed Scan Testing Techniquementioning

confidence: 99%

Power efficient scan testing by exploiting existing error tolerance circuitry in a design

Anastasiou

Tsiatouhas

2014

1Abstract-Timing errors are a major threat in modern integrated circuits. Suitable error tolerance design techniques exist, like Razor, aiming to confront with this situation. However, the silicon area cost of these solutions makes them unattractive for widespread use. In this paper, aiming to broaden the applicability of timing error tolerance techniques, we explore the ability to extend their use for low power scan testing operations. A low power scan version of the Razor technique is presented, which drastically reduces the scan power consumption by eliminating the signal transitions at the input of the combinational logic during the scan operations.

“…Specifically, the amount of time available to a combinational block that lies between two flip flops is fixed. This constrains timing uncertainties within each combinational block [24]. The flip flops are used extensively in all kinds of digital designs as the basic storage elements.…”

Section: Introductionmentioning

confidence: 99%

Clock Gated Single-Edge-Triggered Flip-Flop Design with Improved Power for Low Data Activity Applications

Khan¹,

Beg²

2014

ijeei

In this paper, the proposed flip-flop reduces power consumption by reducing the clock switching power that was wasted otherwise. Unlike many other gated flip-flops, the proposed gated flip-flop has state retention property to save power and to switch circuit between idle and active modes smoothly. The feedback path is also improved in the proposed flip-flop to decrease power dissipation. The proposed clock-gating scheme only requires 4 transistors, thus occupies the small silicon area. Further, the proposed clock gating network can be shared among a group of flip-flops to reduce the power and area overhead of the gating network. The simulation results show that for all supply voltages, the proposed flip-flop has the least power dissipation among all the designs for low switching activities. The proposed flip-flop has up to 7.82 times power improvement than the existing flip-flops. However, for 100% data activity, the proposed FF consumes up to 2.71 times power than the existing flip-flops. The proposed clock gated flip-flop structure is best suited for applications where input signal switching activity is low and speed is not a crucial factor.