Power efficient design of real-time systems based on programmable processors becomes more important as system functionality is increasingly realized through software. This paper presents a powerefficient version of a widely used fixed priority scheduling method. The method yields a power reduction by exploiting slack times, both those inherent in the system schedule and those arising from variations of execution times. The proposed run-time mechanism is simple enough to be implemented in most kernels. Experimental results show that the proposed scheduling method obtains a significant power reduction across several kinds of applications.
Memristor devices based on electrochemical metallization operate through electrochemical formation/dissolution of nanoscale metallic filaments, and they are considered a promising future nonvolatile memory because of their outstanding characteristics over conventional charge-based memories. However, nanoscale conductive paths or filaments precipitated from the redox process of metallic elements are randomly formed inside oxides resulting in unexpected and stochastic memristive switching parameters including the operating voltage and the resistance state. Here, we present the guided formation of conductive filaments in Ag nanocone/SiO nanomesh/Pt memristors fabricated by high-resolution nanotransfer printing. Consequently, the uniformity of the memristive switching behavior is significantly improved by the existence of electric field-concentrator arrays consisting of Ag nanocones embedded in SiO nanomesh structures. This selective and controlled filament growth was experimentally supported by analyzing simultaneously the surface morphology and current-mapping results using conductive atomic-force microscopy. Moreover, stable multi-level switching operations with four discrete conduction states were achieved by the nanopatterned memristor device demonstrating its potential in high-density nanoscale memory devices.
Voltage islands enable core-level power optimization for Systemon-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves island partition creation, voltage level assignment and floorplanning. The task of island partition creation and level assignment have to be done simultaneously in a floorplanning context due to the physical constraints involved in the design process. This leads to a floorplanning problem formulation that is very different from the traditional floorplanning for ASIC-style design.In this paper, we define the problem of architecting voltage islands in core-based designs and present a new algorithm for simultaneous voltage island partitioning, voltage level assignment and physical-level floorplanning. Application of the proposed algorithm to a few benchmark and industrial examples is demonstrated using a prototype tool. Results show power savings of 14%-28%, depending on the constraints imposed on the number of voltage islands and other physical-level parameters.
In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access and data transfer. Thus, buses should be designed and optimized to consume reasonable power while delivering sufficient performance. In this paper, we address bus ordering problems for low-power application-specific systems. A heuristic algorithm is proposed to determine the order in a way that effective lateral component of capacitance is reduced, thereby reducing the power consumed by buses. Experimental results for various examples indicate that the average power saving from 30% to 46.7% depending on capacitance components can be obtained without any circuit overhead.
The analysis and simulation of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the timing aspects of interconnects, power consumption is also important. In this paper, the power distribution analysis of interconnects is studied using a reduced-order model. The relation between power consumption and the poles and residues of a transfer function (either exact or approximated) is derived, and a simple yet accurate driver model is developed, allowing power consumption to be computed efficiently. Application of the proposed method to RC networks is demonstrated using a prototype tool.
We developed a layer‐specific soil‐moisture assimilation scheme using a simulation‐optimization framework, Soil‐Water‐Atmosphere‐Plant model with genetic algorithm (SWAP‐GA). Here, we explored the quantification of the soil hydraulic properties in a layered soil column under various combinations of soil types, vegetation covers, bottom boundary conditions and soil layering using idealized (synthetic) numerical studies and actual field experiments. We demonstrated that soil layers and vertical heterogeneity (layering arrangements) could impact to the uncertainty of quantifying soil hydraulic parameters. We also found that, under layered soil system, when the subsurface flows are dominated by upward fluxes, e.g., from a shallow water table, the solution to the inverse problem appears to be more elusive. However, when the soil profile is predominantly draining, the soil hydraulic parameters could be fairly estimated well across soil layers, corroborating the results of past studies on homogenous soil columns. In the field experiments, the layer‐specific assimilation scheme successfully matched soil moisture estimates with observations at the individual soil layers suggesting that this approach could be applied in real world conditions.
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