Evolution of NAND Flash Memory: From 2D to 3D as a Storage Market Leader

Kim, Hyun Suk; Ahn, Su-Jin; Shin, Youngsoo; Lee, Kyu Pil; Jung, Eun-Sung

doi:10.1109/imw.2017.7939081

Cited by 106 publications

(52 citation statements)

References 9 publications

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“…In spite of all efforts to limit electrostatic interference, it became probably the most relevant reliability issue for the last 2-D NAND technologies and a strong relief to it was offered only by the transition to 3-D arrays. In this regard, a reduction of cell-to-cell interference by about the 80% is typically ascribed to this transition [14], [21], as shown in Fig. 13.…”

Section: A Magnitude Of the Most Relevant Issues For Array Reliabilitymentioning

confidence: 80%

“…First of all, they allowed to use conventional single-patterning ArF immersion lithography, whose minimum feature size is ∼40 nm [20], for most of the process flow, limiting the need for double-patterning techniques [21]. Then, they allowed to reduce the impact on array reliability and performance of the main physical issues that constrained the operation of 2-D arrays [10], [14], [21], [22], thanks also to a cell size for oxide/nitride/oxide and IPD stands for interpoly dielectric). The oxide layers isolating the WLs and the gate-stack in-betweeen the WLs and the silicon channels are not shown in (a) for better figure readability.…”

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confidence: 99%

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Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Compagnoni

Spinelli

2019

IEEE Trans. Electron Devices

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This paper reviews what changed in the reliability of NAND Flash memory arrays after the paradigm shift in technology evolution determined by the transition from 2-D to 3-D integration schemes. Starting from a quick glance at the fundamentals of raw array reliability, the reasons for its worsening with the evolution of 2-D technologies will be discussed, focusing on the physical phenomena which contributed more to that outcome. By exploring the dependence of the magnitude of these phenomena on cell and array parameters, the abrupt improvements achieved from the 3-D transition in terms of raw array reliability will then be explained, highlighting also that these improvements were turned into new opportunities for the technology. Finally, the physical issues specific to 3-D arrays will be addressed, providing a glimpse of the challenges that the NAND Flash technology will have to face from the standpoint of array reliability in the near future. Index Terms-3-D NAND Flash arrays, Flash memories, semiconductor device modeling, semiconductor device reliability. I. INTRODUCTIONT HE NAND Flash technology has become, today, the undisputed leader in the nonvolatile memory market, largely overcoming the hard-disk drive (HDD) technology in terms of revenues [1]. This outcome has been determined by the capability of the NAND Flash solution to address quite a variety of applications better than any other storage technology, thanks to successful tradeoffs among cost, performance, and reliability. At the heart of all that there is, of course, the possibility to steadily increase the integration density of the NAND array and, in turn, the memory capacity per chip. This is clearly proved in Fig. 1 in terms of gross bit storage density (GBSD), i.e., the ratio between the storage capacity and the total chip area, of the NAND Flash chips presented at the IEEE International Solid-State Circuits Conference (IEEE ISSCC) since 2001 (see [2] for further details on the analysis methodology).Up to ∼2015, the GBSD increase was achieved, first of all, through a constant pace miniaturization of the memory cells

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Section: A Magnitude Of the Most Relevant Issues For Array Reliabilitymentioning

confidence: 80%

mentioning

confidence: 99%

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Compagnoni

Spinelli

2019

IEEE Trans. Electron Devices

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“…The bit error rate of the MSB page is obviously increasing with the P/E cycles. When the P/E cycles are 500 and 1000 times, the original bit error rate of MSB page and LSB page is closer, about -4 5 10  . With the increase in P/E cycles, the original bit error rates of the CSB page and LSB page increase slowly, while the original bit error rate of the MSB page rises sharply.…”

Section: Algorithm Verification and Analysismentioning

confidence: 97%

“…Depending on the bit number per storage cell, NAND flash memory is divided into three types, namely Single-Level Cell (short for SLC, 1 bit per storage cell), Multi-Level Cell (short for MLC, 2 bits per storage cell), Triple-Level Cell (short for TLC, 3 bits per storage cell). At present, the storage structure of NAND flash memory has changed from a traditional plane structure to a three-dimensional structure [4][5][6][7], which further improves the storage density. With the increase in storage density, data reliability [8] of flash memory has decreased [9].…”

Section: Introductionmentioning

confidence: 99%

Program Disturb Research and Error Avoidance Algorithm Design of 3D-TLC NAND Flash Memory

Yang¹

2018

IJPE

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This paper focuses on finding, settling and reducing the program disturb error of 3D-TLC NAND flash memory. Experimental analysis of the FPGA test platform determines characteristics of the program disturb error. The program disturb error makes the state shift rate of storage cells lose balance. MSB, CSB and LSB pages have unbalanced bit error ratio and bit error rate distribution. The page program disturb bit error is unbalanced as the number of program/erase cycles changes. Based on the experimental results of the error rate imbalance, an error avoidance algorithm is designed, which can shift the data state that is subject to program disturb to one that is not vulnerable to program disturb. The test results show that the algorithm can reduce the error rate of program disturb by 20% to 90%. In this sense, the program disturb error phenomenon found and error avoidance algorithm designed in this paper are helpful for improving the reliability of 3D-TLC NAND flash memory.

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“…N AND flash-based solid-state drives (SSDs) are secondary storage devices used in various computing environments, from mobile devices to server systems. It is rapidly replacing the magnetic-based hard disk drives owing to its advantages, such as high random access performance, low power requirement, small form factor, and cost-per-bit reduction that has continued for decades [1], [2]. However, SSDs possess some disadvantages, such as latency variability [3]- [7], suboptimal resource utilization [8], [9], log-on-log [10], [11], and long-tail latency [12].…”

Section: Introductionmentioning

confidence: 99%

Improving Write Performance Through Reliable Asynchronous Operation in Physically-Addressable SSD

et al. 2020

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Physically-addressable solid-state drives (PASSDs) are secondary storage devices that provide a physical address-based interface for a host system to directly control NAND flash memory. PASSDs overcome the shortcomings such as latency variability, resource under-utilization, and log-on-log that are associated with legacy SSDs. However, in some operating environments, the write response time significantly increases because the PASSD reports the completion of a host write command synchronously (i.e., write-through) owing to reliability problems. It contrasts asynchronous processing (i.e., write-back), which reports a completion immediately after data are received in a high-performance volatile memory subsequently used as a write buffer to conceal the operation time of NAND flash memory. Herein, we propose a new scheme that guarantees write reliability to enable a reliable asynchronous write operation in PASSD. It is designed to use a large-granularity mapping table for minimizing the memory requirements and performing internal operations at an idle time to avoid response delays. Results demonstrate that the proposed PASSD reduces the average write response time by up to 88% and guarantees reliability without performance degradation.

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Evolution of NAND Flash Memory: From 2D to 3D as a Storage Market Leader

Cited by 106 publications

References 9 publications

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Program Disturb Research and Error Avoidance Algorithm Design of 3D-TLC NAND Flash Memory

Improving Write Performance Through Reliable Asynchronous Operation in Physically-Addressable SSD

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