Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation

Abstract

Aggressive reduction of timing margins, called timing speculation, is an effective way of reducing the supply voltage for a pipeline circuit and thereby its power consumption. However, probability of timing error increases with the voltage scaling and hence, the errors must be corrected with small cycle penalty. We introduce an improved Razor flip-flop which makes more effective use of its shadow latch, so that a pipeline stage can correct an error while continuing to receive data. This avoids the need for repeated clock gating when timing errors happen simultaneously at different stages, or when an error persists. The new flip-flop also facilitates time-borrowing. Our technique uses less energy than the state-of-the art technique, and the energy saving increases with pipeline length: with 10 stages, 4-9% smaller energy is used.

TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor

“…Since the timing error is detected after the system is incorrect, error correction is mandatory. Generally, error correction methods include instruction replay at halved clock frequency [5], counterflow pipelining [11], clock gating [3,6], and so on. However, the above error correction scenarios incur large performance loss.…”

“…In our work, since the clock on each pipeline still exists, our proposed TBCT method does not need extra MCG or VE signal [6,10] and reduce the complexity of implementation.…”

“…On-line Error Detection and Correction (EDC) has proved to be a promising technique to mitigate the redundant timing margin [3]. The prototype of the EDC system is Razor circuit which detects the timing error then corrects it [4,5,6]. Unfortunately, removing timing margin increases the probability of timing errors due to variation, which in turn leads to the high error rates and massive cycles for system recovering from timing errors.…”

“…Typically, instruction replay has extra 3N cycles penalties, where N is the number of pipeline stage [5]. Therefore, there is an urgent to reducing the recovery overhead as much as possible [6,7,8,9,10].…”

Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines

“…Two major design approaches have been proposed to address the issues with such large timing margins [2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26].…”