PSTA-based branch and bound approach to the silicon speedpath isolation problem

Abstract

The lack of good "correlation" between pre-silicon simulated delays and measured delays on silicon (silicon data) has spurred efforts on so-called silicon debug. The identification of speedlimiting paths, or simply speedpaths, in silicon debug is a crucial step, required for both "fixing" failing paths and for accurate learning from silicon data. We propose using characterized, presilicon, variational timing models to identify speedpaths that can best explain the observed delays from silicon measurements. Delays of all logic paths are written as affine functions of process parameters, called hyperplanes, and a branch and bound approach is then applied to find the "best" path combinations. Our method has been tested on a set of ISCAS-89 circuits and the results show that it accurately identifies the speedpaths in most cases, and that this is achieved in a very efficient manner.

SAT-based speedpath debugging using X traces

“…The post-silicon timing validation is started by applying the test vectors to the chip while clock shrinking is performed [16] [17]. If an error is observed on the outputs or registers, the error is returned as an Erroneous Trace (ET).…”

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

“…For a fabricated chip, the degree of variation might be such that the delays of some of the paths exceed their timing requirements. We assume such paths are isolated and their delays are measured as discussed in [1], [3], [5], [7], [9]. Moreover, we assume the delays of additional speedpaths are also measured.…”

“…Note that our focus is on the segment identification problem, assuming the failing speedpaths are provided. We assume isolation of failing speedpaths is done using existing works such as [1], [3], [5], [7], while post-silicon path delay measurement is done using existing techniques such as [9].…”

“…We declare an instance to be a "failing sample" if at least one path in PC fails the timing. Recall, we assume failing paths are identified and isolated using existing techniques, such as [7]. Here, we use our golden model to localize failing paths for a variation instance, while the representative paths are determined once and remain the same over all variation instances.…”

“…In [5], a manuallyguided technique is used to isolate failing speedpaths, via combination of techniques including clock shrinkage and using a debug tester. In [7], a branch-and-bound technique for isolation of speedpaths is proposed which is based on parameterized static timing analysis.…”