Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor

Magklis, Grigorios; Scott, Michael L.; Semeraro, Greg; Albonesi, David H.; Dropsho, Steven

doi:10.1145/859619.859621

Cited by 47 publications

(38 citation statements)

References 5 publications

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“…Most DVFS techniques proposed to date typically apply to single processors such as the Intel XScale or Pentium-M [6,3,7]. Some recent work has looked at processors with several internal clock domainsmultiple-clock-domain (MCD) processors [10,15,16,19,20]-but are restricted to local solutions in which each domain is considered separately. Such local, per-tile DVFS techniques lead to unstable DVFS control of CMPs processing multithreaded applications, worsening overall chip power-performance (See Section 2).…”

Section: Introductionmentioning

confidence: 99%

Coordinated, distributed, formal energy management of chip multiprocessors

Juang

Peh

et al. 2005

Proceedings of the 2005 International Symposium on Low Power Electronics and Design - ISLPED '05

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Designers are moving toward chip-multiprocessors (CMPs) to leverage application parallelism for higher performance while keeping design complexity under control. However, to date, no power management techniques have been proposed for coordinated power control of multiple processor cores.In this paper, we illustrate how the use of local, per-tile dynamic voltage and frequency scaling (DVFS) techniques can result in tiles counteracting each others' power management policies, significantly hurting chip power-performance. We then propose a coordinated DVFS scheme for CMPs, which eliminates the oscillations and ensures efficient and resilient DVFS control. Specifically, our proposed technique incorporates thread information collected at runtime across the chip. In addition, by extending a control-theoretic local DVFS control technique toward DVFS for chip-multiprocessors, our technique prescribes DVFS settings formally at each tile, thus ensuring stable, distributed, coordinated DVFS control of a CMP. Experimental results show that our technique achieves a 15.5% improvement in energy-delay product over a CMP with no DVFS control, and a 7% improvement in energy-delay product against the latest state-of-the-art local DVFS scheme.

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Section: Introductionmentioning

confidence: 99%

Coordinated, distributed, formal energy management of chip multiprocessors

Juang

Peh

et al. 2005

Proceedings of the 2005 International Symposium on Low Power Electronics and Design - ISLPED '05

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“…Globally Asynchronous Locally Synchronous (GALS) [2], which is a compromise between asynchronous systems and synchronous systems, has been focused on. Most current researches on GALS are based on superscalars [3,4,5,6,7,8], and not been applied to EPIC architecture, because there are much difficulties in its implementation. For example, the uncertainty of asynchronous communication brings significant challenges for data dependence and instruction completion in order in EPIC.…”

Section: Introductionmentioning

confidence: 99%

The Implementation and Design of a Low-Power Clock Distribution Microarchitecture

Jiang

Zeng

Chen

et al. 2007

2007 International Conference on Networking, Architecture, and Storage (NAS 2007)

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The high clock frequency of current high-performan microprocessors brings the significant challenge for the microprocessors' power. The multiple clock domain (MCD) technique is a new clock distribution technique, which retains the benefits of synchronous designs and avoids the problems due to global clock to reduce the power of the clock distribution. Most present studies of MCD are only based on superscalar architectures. In this paper, a low-power clock distribution micro-architecture, named MCDE, the MCD microarchitecture based on explicitly parallel instruction computing (EPIC) is designed and implemented. Furthermore, a series of experiments on our design have been done to evaluate it. The experimental results show that, using a MCDE microarchitecture with a fine-grained dynamic frequency scaling algorithm, can effectively decrease the microprocessor power by 40%, compared with the conventional EPIC processor with only one clock domain.

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“…A lot of works have been done in order to save the energy dissipated in embedded systems [1,2,3]. They gave many ideas of how to improve the power efficient of software.…”

Section: Related Workmentioning

confidence: 99%

“…(1) And they use the following expression to predicate the main memory power consumption: Powermem = 1 …”

Section: Powercpu = 1 (Ifetchmiss) + 2 (Datadep) + 3 (Datatlbmiss) + mentioning

confidence: 99%

Power Estimation for an Application on the Xscale Platform Using PMU events

Huang

Qianjie

International Conference on Digital Telecommunications (ICDT'06)

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In this paper we present a new power estimation model for an application above the operation system. This method uses the performance monitor unit (PMU) events to predicate the power an application consumed. This model maps the hardware events to the power dissipation for the processor and memory when a specific application is running. We use some diffusely selected benchmarks to test our model. The result shows that it is a exact method to estimation the power consumption for any application above the OS.

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Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor

Abstract: Abstract

Cited by 47 publications

References 5 publications

Coordinated, distributed, formal energy management of chip multiprocessors

Coordinated, distributed, formal energy management of chip multiprocessors

The Implementation and Design of a Low-Power Clock Distribution Microarchitecture

Power Estimation for an Application on the Xscale Platform Using PMU events

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