Coordinated, distributed, formal energy management of chip multiprocessors

Juang, Philo; Wu, Qiang; Peh, Li-Shiuan; Martonosi, Margaret; Clark, Douglas W.

doi:10.1145/1077603.1077637

Cited by 57 publications

(19 citation statements)

References 28 publications

(27 reference statements)

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“…Juang et al [16] argue for coordinated formal control-theoretic methods to manage energy efficiency in multi-core systems. Isci et al [15] introduce the problem of trying to maximize total throughput under a chip-wide power constraint by dynamically tuning DVFS to workload characteristics and develop the effective (but limited in scalability) brute force MaxBIPS algorithm.…”

Section: Related Workmentioning

confidence: 99%

Scalable thread scheduling and global power management for heterogeneous many-core architectures

Winter

Albonesi

Shoemaker

2010

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques

124

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Future many-core microprocessors are likely to be heterogeneous, by design or due to variability and defects. The latter type of heterogeneity is especially challenging due to its unpredictability. To minimize the performance and power impact of these hardware imperfections, the runtime thread scheduler and global power manager must be nimble enough to handle such random heterogeneity. With hundreds of cores expected on a single die in the future, these algorithms must provide high power-performance efficiency, yet remain scalable with low runtime overhead.This paper presents a range of scheduling and power management algorithms and performs a detailed evaluation of their effectiveness and scalability on heterogeneous many-core architectures with up to 256 cores. We also conduct a limit study on the potential benefits of coordinating scheduling and power management and demonstrate that coordination yields little benefit. We highlight the scalability limitations of previously proposed thread scheduling algorithms that were designed for small-scale chip multiprocessors and propose a Hierarchical Hungarian Scheduling Algorithm that dramatically reduces the scheduling overhead without loss of accuracy. Finally, we show that the high computational requirements of prior global power management algorithms based on linear programming make them infeasible for many-core chips, and that an algorithm that we call Steepest Drop achieves orders of magnitude lower execution time without sacrificing power-performance efficiency.

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Section: Related Workmentioning

confidence: 99%

Scalable thread scheduling and global power management for heterogeneous many-core architectures

Winter

Albonesi

Shoemaker

2010

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques

124

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“…In this section, we propose and discuss two simple binning metrics that recognize the frequency effects of process variation. We assume that individual cores are testable and runnable at independent operating frequencies [22], [23], [24], [25], [26], [27] though our discussion and analysis would continue to hold in other scenarios.…”

Section: Binning Metricsmentioning

confidence: 99%

Variation-aware speed binning of multi-core processors

Sartori

Pant

Kumar

et al. 2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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Abstract-Number of cores per multi-core processor die, as well as variation between the maximum operating frequency of individual cores, is rapidly increasing. This makes performance binning of multi-core processors a non-trivial task. In this paper, we study, for the first time, multi-core binning metrics and strategies to evaluate them efficiently. We discuss two multi-core binning metrics with high correlation to processor throughput for different types of workloads and different process variation scenarios. More importantly, we demonstrate the importance of leveraging variation model data in the binning process to significantly reduce the binning overhead with a negligible loss in binning quality. For example, we demonstrate that the performance binning overhead of a 64-core processor can be decreased by 51% and 36% using the proposed variationaware core clustering and curve fitting strategies respectively. Experiments were performed using a manufacturing variation model based on real 65nm silicon data.

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“…Chen et al [7] propose an approximation algorithm to partition tasks with different power consumption functions. Juang et al [13] show a coordinated DVS scheme for chip multiprocessor. None of these studies have taken advantage of the probabilistic workload information.…”

Section: Dvs For Multiprocessormentioning

confidence: 99%

Energy-aware scheduling for real-time multiprocessor systems with uncertain task execution time

Xian¹,

Lu²,

Li³

2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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This paper presents an energy-aware method to schedule multiple real-time tasks in multiprocessor systems that support dynamic voltage scaling (DVS). The key difference from existing approaches is that we consider the probabilistic distributions of the tasks' execution time to partition the workload for better energy reduction. We analyze the problem of energy-aware scheduling for multiprocessor with probabilistic workload information and derive its mathematical formulation. As the problem is NP-hard, we present a polynomial-time heuristic method to transform the problem into a probability-based load balancing problem that is then solved with worst-fit decreasing bin-packing heuristic. Simulation results with synthetic, multimedia, and stereovision tasks show that our method saves significantly more energy than existing methods.

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Coordinated, distributed, formal energy management of chip multiprocessors

Cited by 57 publications

References 28 publications

Scalable thread scheduling and global power management for heterogeneous many-core architectures

Scalable thread scheduling and global power management for heterogeneous many-core architectures

Variation-aware speed binning of multi-core processors

Energy-aware scheduling for real-time multiprocessor systems with uncertain task execution time

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