Scalable thread scheduling and global power management for heterogeneous many-core architectures

Abstract

Future many-core microprocessors are likely to be heterogeneous, by design or due to variability and defects. The latter type of heterogeneity is especially challenging due to its unpredictability. To minimize the performance and power impact of these hardware imperfections, the runtime thread scheduler and global power manager must be nimble enough to handle such random heterogeneity. With hundreds of cores expected on a single die in the future, these algorithms must provide high power-performance efficiency, yet remain scalable with low runtime overhead.This paper presents a range of scheduling and power management algorithms and performs a detailed evaluation of their effectiveness and scalability on heterogeneous many-core architectures with up to 256 cores. We also conduct a limit study on the potential benefits of coordinating scheduling and power management and demonstrate that coordination yields little benefit. We highlight the scalability limitations of previously proposed thread scheduling algorithms that were designed for small-scale chip multiprocessors and propose a Hierarchical Hungarian Scheduling Algorithm that dramatically reduces the scheduling overhead without loss of accuracy. Finally, we show that the high computational requirements of prior global power management algorithms based on linear programming make them infeasible for many-core chips, and that an algorithm that we call Steepest Drop achieves orders of magnitude lower execution time without sacrificing power-performance efficiency.

A Study on Various Security Aspects in Cloud Policy Oriented Architecture

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Adaptive Post-silicon Server Validation using Machine Learning

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Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores

“…In [30], Winter et al explore thread scheduling and global power management techniques in AMPs. They compare different algorithms like brute force, greedy and local search for thread scheduling.…”

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“…The reconfiguration allows the cores to match their hardware computation capabilities to the requirements of the executing workloads. 2) A novel hardware-based runtime algorithm to concurrently and non-invasively predict the performance per watt of applications while previously proposed dynamic schemes [30], [37] required sampling to determine the thread to core assignment. When the performance monitoring indicates that reconfiguration may be beneficial, our scheme either triggers a swap of the applications between cores, or performs a resource morphing, or reverts to the baseline configuration.…”