Variation-aware speed binning of multi-core processors

Abstract

Abstract-Number of cores per multi-core processor die, as well as variation between the maximum operating frequency of individual cores, is rapidly increasing. This makes performance binning of multi-core processors a non-trivial task. In this paper, we study, for the first time, multi-core binning metrics and strategies to evaluate them efficiently. We discuss two multi-core binning metrics with high correlation to processor throughput for different types of workloads and different process variation scenarios. More importantly, we demonstrate the importance of leveraging variation model data in the binning process to significantly reduce the binning overhead with a negligible loss in binning quality. For example, we demonstrate that the performance binning overhead of a 64-core processor can be decreased by 51% and 36% using the proposed variationaware core clustering and curve fitting strategies respectively. Experiments were performed using a manufacturing variation model based on real 65nm silicon data.

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings

“…Furthermore, with the emergence of multi-core technology, intra-die variation has also become an issue. To minimize the overheads of guardbanding, recent efforts have shown that exploiting the inherent variation in devices [6], [7] yields significant improvements in overall system performance.…”

On the Design of Real-Time Systems on Multi-Core Platforms under Uncertainty

“…There are a few strategies that are commonly adopted to combat the process variation problems. For example, performance (or speed) binning approach, which intends to pack processors into different classes based on their maximum operating frequencies, is a common method for profit maximization in the presence of frequency variation [37,140]. Performance binning is good for single core chips, however, it cannot capture the characteristic of a multi-core system.…”

“…For example, performance/speed binning technique has been widely used to cluster chips with similar performance (e.g., frequency, leakage power) [141,122]. However, this approach didn't consider within-die variation.…”

“…[141]) to cluster chips with similar performance. As a result, even in the presence of large manufacturing variations, processors of the same grade have less performance variations.…”

“…Besides extensive work on layout and device level, there are increasing research efforts to address the process variation problem from architecture and system level. For example, performance binning technique is proposed to cluster chips with similar performance [141,122]. However, this approach cannot deal with process variation of different cores within the same chip.…”