The Implementation and Design of a Low-Power Clock Distribution Microarchitecture

Abstract

The high clock frequency of current high-performan microprocessors brings the significant challenge for the microprocessors' power. The multiple clock domain (MCD) technique is a new clock distribution technique, which retains the benefits of synchronous designs and avoids the problems due to global clock to reduce the power of the clock distribution. Most present studies of MCD are only based on superscalar architectures. In this paper, a low-power clock distribution micro-architecture, named MCDE, the MCD microarchitecture based on explicitly parallel instruction computing (EPIC) is designed and implemented. Furthermore, a series of experiments on our design have been done to evaluate it. The experimental results show that, using a MCDE microarchitecture with a fine-grained dynamic frequency scaling algorithm, can effectively decrease the microprocessor power by 40%, compared with the conventional EPIC processor with only one clock domain.