PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices

Abstract

Evaluation of novel devices in the context of circuits is crucial to identifying and maximizing their value. We propose a new framework, Pareto optimization-based circuit-level evaluator for emerging device (PROCEED), that uses comprehensive performance, power, and area metrics for accurate device-circuit coevaluation through optimization of digital circuit benchmarks. The PROCEED assesses technology suitability over a wide operating region (megahertz to gigahertz) by leveraging available circuit knobs (threshold voltage assignment, power management, sizing, and so on). It improves the benchmark accuracy by 3× to 115× compared with the existing methods while offering orders of magnitude improvements in runtime over full physical design implementation flows. To illustrate the PROCEED's capabilities, we deploy it to assess emerging technologies, including novel tunneling field-effect transistors, compared with conventional silicon CMOS. As a further illustration, we extend PROCEED to evaluate future heterogeneous integration of varied devices onto the same silicon substrate. Index Terms-Circuit-level device evaluation, Pareto optimization, silicon-on-insulator (SOI), simulation-based optimization, tunneling field-effect transistor (TFET).

Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

“…GP libraries are targeted towards energy-delay optimized designs while LPE libraries are targeted towards low performance but energy efficient designs. We used PROCEED [33], a circuit level emulator to find the optimal power-delay pareto curve for CORTEX-M0. A wide operation region (MHz to GHz) was accessed for both GP and LPE technologies.…”

Assessing Benefits of a Buried Interconnect Layer in Digital Designs

“…TCAD simulations on entire library will take infinite time and is out of the scope of this paper. We use a simplified logic gate stage ( Figure 9) as in [22], [23], which contains a driving gate (e.g., inverter), a wire load (resistance and capacitance), and a gate load (e.g., inverter), to simulate the propagation delay change of standard cells after using the buried layer. The accuracy of the simplified gate model for chip-level speed estimation has been verified in [22], [23] against synthesis, placement, and routing.…”

“…We use a simplified logic gate stage ( Figure 9) as in [22], [23], which contains a driving gate (e.g., inverter), a wire load (resistance and capacitance), and a gate load (e.g., inverter), to simulate the propagation delay change of standard cells after using the buried layer. The accuracy of the simplified gate model for chip-level speed estimation has been verified in [22], [23] against synthesis, placement, and routing. In our library, when a cell is redesigned with the additional buried layer, total copper wire length (M 1 and M 2 ) is reduced and the use of Tungsten (M -1 and CA) increases due to the routes that get relocated to M -1 from M and M .…”