Assessing Benefits of a Buried Interconnect Layer in Digital Designs

Abstract

ABSTRACT-In sub-15nm technology nodes, local metal layers have witnessed extremely high congestion leading to pin-accesslimited designs, and hence affecting the chip area and related performance. In this work we assess the benefits of adding a buried interconnect layer below the device layers for the purpose of reducing cell area, improving pin access and reducing chip area. After adding the buried layer to a projected 7nm standard cell library, results show ~9-13% chip area reduction and 126% pin access improvement. This shows that buried interconnect, as an integration primitive, is very promising as an alternative method to density scaling.

Buried Powered 4t Sram with Improved Write Margin

“…Buried power rails are employed for the interconnection between the standard cells. The profit of utilizing the buried powered rail [2] in SRAM is surveyed in this paper. The high-aspect-proportion of Ruthenium (Ru) is utilized in this design.…”