Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

Abstract

Abstract-In this paper, we describe the performance and power benefits of our Fine Pitch integration scheme on a Silicon Interconnect Fabric (Si IF). Here we propose a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet to interconnect fabric assembly. We show the dramatic improvements in bandwidth, latency, and power are achievable through our integration scheme where small dielets (1-25 mm 2 ) are attached to a rigid Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 μm) and short inter-die distance (50-500 μm) using solderless metal-to-metal thermal compression bonding (TCB). Our simulations show that links in the Si-IF with short wire-lengths (<500 μm) have excellent signal transfer characteristics with low channel loss (<-2 dB) and low cross-talk (<-15 dB). With fine interconnect pitches (<10 μm), our scheme can achieve >5-25x improvement in data bandwidth. This can improve system performance (>20x) when compared to PCB-style integration and may even approach single die SoC metrics in some cases. Furthermore our protocol is simple and non-proprietary. We show that this scheme enables heterogeneous system integration using a dielet based assembly method and provides significant reduction in design and validation cost.System-level analysis of heterogeneous integration scheme promises power benefits of more than 15% even for very small systems.

A Case for Packageless Processors

“…Thus, RC delay would also be smaller. Using detailed multi-physics and SPICE simulations, we verified that the links can be switched at 2-4 GHz, while consuming <0.3 pJ/bit using very simple I/O drivers [28].…”

“…Rigid (polish-able) silicon wafer and copper pillar based IOs (bonded using thermal-compression bonding (TCB) at tight pitches) in Si-IF address both these limitations. 1 Since the interconnect wires on Si-IF are manufactured using standard back-end process, the wire pitch can scale like normal top-level metal in SoCs and well below 2 µm [27], [28]. This technology thus bridges the gap between the SoC level interconnects and system-level interconnects and allows a processor die to support the required number of I/O and power pins even without a package.…”

“…More details on Si-IF manufacturing (e.g., patterning, die alignment, bonding, etc.) and characterization can be found in [27] and [28]. In this section, we consider a baseline many-core processor architecture and evaluate the impact on memory bandwidth, TDP, and area if the processor's package is removed and the processor die is integrated using silicon interconnect fabric.…”

Advanced Packaging and Heterogeneous Integration to Reboot Computing

“…Simple buffer based drivers and smaller capacitive load on each interconnect wire is expected to lower the energy per bit of communication as well. Our simulation analysis shows that <0.3 pJ/bit can be achieved on SiIF versus >5 pJ/bit and >10 pJ/bit required for interposer links and PCB links respectively [17].…”

“…Without ESD, the latencies can go as low as 30-40ps. Detailed modelling and analysis of the interconnect characteristic is provided in [17]. Simple buffer based drivers and smaller capacitive load on each interconnect wire is expected to lower the energy per bit of communication as well.…”