A Case for Packageless Processors

Abstract

Demand for increasing performance is far outpacing the capability of traditional methods for performance scaling. Disruptive solutions are needed to advance beyond incremental improvements. Traditionally, processors reside inside packages to enable PCB-based integration. We argue that packages reduce the potential memory bandwidth of a processor by at least one order of magnitude, allowable thermal design power (TDP) by up to 70%, and area efficiency by a factor of 5 to 18. Further, silicon chips have scaled well while packages have not. We propose packageless processors -processors where packages have been removed and dies directly mounted on a silicon board using a novel integration technology, Silicon Interconnection Fabric (Si-IF). We show that Si-IF-based packageless processors outperform their packaged counterparts by up to 58% (16% average), 136% (103% average), and 295% (80% average) due to increased memory bandwidth, increased allowable TDP, and reduced area respectively. We also extend the concept of packageless processing to the entire processor and memory system, where the area footprint reduction was up to 76%.• We make a case for packageless processors. We argue that modern processor packages greatly hinder performance, bandwidth, and energy efficiency scaling. Eliminating packages can enable us to recoup the lost performance, bandwidth, and energy efficiency. • We present Si-IF, a novel integration technology, as a potential replacement for PCB-based integration and as the enabling technology for packageless processing. • We quantify the bandwidth, TDP, and area benefits from packageless processing. We show that up to one to two orders of magnitude, 70%, and 5-18x benefits respectively, are possible over conventional packaged processors. These benefits translate into up to 58% (16% average), 136% (103% average), and 295% (80% average) performance benefits, respectively, for our benchmarks. • We also extend the concept of packageless processing to the entire system on the board; reduction in system-level footprint was up to 76%.

Wave Propagation and Channel Modeling in Chip-Scale Wireless Communications: A Survey From Millimeter-Wave to Terahertz and Optics

“…Fourth, it is crucial to understand packaging options at the chip level as they are relevant to the intra-chip propagation. Traditionally, flip-chip packaging and wire bonding have been the most common, although multiple custom variants and alternatives exist depending on the final application [31], [32]. Flip-chip packaging is generally preferred in the multiprocessor context due to its lower inductance and higher power/bandwidth density [33].…”

Channel Characterization for Chip-scale Wireless Communications within Computing Packages

“…Although a recent work suggests a packageless architecture [37], dies have historically included a package to (i) act as a space transformer for I/O pins, provide mechanical support to the dies, and (iii) for ease of testability and repairability. Some packages include a molding compound around the chip to improves mechanical stability [36], but its typically poor thermal conductivity discourages its use in hot architectures.…”

“…Some packages include a molding compound around the chip to improves mechanical stability [36], but its typically poor thermal conductivity discourages its use in hot architectures. In most cases, even the packageless one [37], the die can be contacted directly by a Thermal Interface Material (TIM) with a metallic heat sink on top, avoiding the use of the molding compound. This work considers a flip-chip package with solder bumps.…”

System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms

“…A second key challenge is that communication interfaces may be incompatible between chiplets, with various chiplets in the same package implementing different communication protocols, in addition to having different bandwidth and power requirements [13]. Although various chiplet-based interconnect protocols have been proposed [6,14,17,18], standardization efforts are still in their infancy and are not widely adopted [21].…”