Wafer‐Scale Integration

Abstract

The key challenges of on‐chip integration, including limited scalability, high cost, difficulty to maintain profitable yield, and increased thermal management complexity, suggest that additional avenues for scaling should be explored. Wafer‐scale integration is the extension of the system‐on‐chip approach to ultralarge systems. A comprehensive review of this transition from the standpoint of packaging, thermal management, and system integration is presented in this article. The benefits and challenges of wafer‐scale integration are discussed. Silicon interconnect fabric, a promising platform for high‐performance heterogeneous wafer‐scale integration, is introduced.