1989
DOI: 10.1016/0022-0248(89)90170-x
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Present status of solid phase epitaxy of vacuum-deposited silicon

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Cited by 30 publications
(6 citation statements)
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“…Defect etching of the sample confirms this observation. Since the crystal quality of SPE grown silicon depends on crystal orientation [29], we compared the etch pit density of five grains that extend from region I to region II in Fig. 5.…”
Section: Cleaning Efficiencymentioning
confidence: 99%
“…Defect etching of the sample confirms this observation. Since the crystal quality of SPE grown silicon depends on crystal orientation [29], we compared the etch pit density of five grains that extend from region I to region II in Fig. 5.…”
Section: Cleaning Efficiencymentioning
confidence: 99%
“…Low-temperature (≤800°C) solid phase epitaxy (SPE) of a-Si by using AIC poly-Si seed layer deposited on glass substrate is a promising approach to obtain poly-Si thin films with high quality [20]. The most significant advantage of this technique is; the AIC poly-Si seed layer has large grain sizes and SPE technique is processed on this seed layer, the final grain sizes of the films are larger than the grain size of the films produced by SPC method [21].…”
Section: Accepted Manuscriptmentioning
confidence: 99%
“…One of the most promising techniques for device grade SOI suitable for three-dimensional integrated circuits is Epitaxial Lateral Overgrowth (ELO), which has been realised using Chemical Vapour Deposition (CVD) [1], Solid Phase Epitaxy (SPE) [2], and Liquid Phase Epitaxy (LPE) [3][4][5][6]. One of the most promising techniques for device grade SOI suitable for three-dimensional integrated circuits is Epitaxial Lateral Overgrowth (ELO), which has been realised using Chemical Vapour Deposition (CVD) [1], Solid Phase Epitaxy (SPE) [2], and Liquid Phase Epitaxy (LPE) [3][4][5][6].…”
mentioning
confidence: 99%
“…One of the most promising techniques for device grade SOI suitable for three-dimensional integrated circuits is Epitaxial Lateral Overgrowth (ELO), which has been realised using Chemical Vapour Deposition (CVD) [1], Solid Phase Epitaxy (SPE) [2], and Liquid Phase Epitaxy (LPE) [3][4][5][6]. The disadvantage of these techniques for SOI circuits is their low overgrowth width of only about 20 #m in the case of CVD [1] and 7 #m in the case of moderately doped SPE materials [2]. The disadvantage of these techniques for SOI circuits is their low overgrowth width of only about 20 #m in the case of CVD [1] and 7 #m in the case of moderately doped SPE materials [2].…”
mentioning
confidence: 99%