Predictive Modeling of the NBTI Effect for Reliable Design

Bhardwaj, Sarvesh; Wang, Wenping; Vattikonda, Rakesh; Cao, Yu; Vrudhula, Sarma

doi:10.1109/cicc.2006.320885

Cited by 347 publications

(268 citation statements)

References 7 publications

Supporting

Mentioning

263

Contrasting

Order By: Relevance

“…The static NBTI/PBTI corresponds to the case when the PMOS/NMOS transistor is under constant stress. In this case, ∆V th due to NBTI/PBTI at time t can be expressed, according to [14], as:…”

Section: Modeling Bti-induced Cmos Device Agingmentioning

confidence: 99%

Optimally Fortifying Logic Reliability through Criticality Ranking

et al. 2015

View full text Add to dashboard Cite

With CMOS technology aggressively scaling towards the 22-nm node, modern FPGA devices face tremendous aging-induced reliability challenges due to bias temperature instability (BTI) and hot carrier injection (HCI). This paper presents a novel anti-aging technique at the logic level that is both scalable and applicable for VLSI digital circuits implemented with FPGA devices. The key idea is to prolong the lifetime of FPGA-mapped designs by strategically elevating the V DD values of some LUTs based on their modular criticality values. Although the idea of scaling V DD in order to improve either energy efficiency or circuit reliability has been explored extensively, our study distinguishes itself by approaching this challenge through an analytical procedure, therefore being able to maximize the overall reliability of the target FPGA design by rigorously modeling the BTI-induced device reliability and optimally solving the V DD assignment problem. Specifically, we first develop a systematic framework to analytically model the reliability of an FPGA LUT (look-up table), which consists of both RAM memory bits and associated switching circuit. We also, for the first time, establish the relationship between signal transition density and a LUT's reliability in an analytical way. This key observation further motivates us to define the modular criticality as the product of signal transition density and the logic observability of each LUT. Finally, we analytically prove, for the first time, that the optimal way to improve the overall reliability of a whole FPGA device is to fortify individual LUTs according to their modular criticality. To the best of our knowledge, this work is the first to draw such a conclusion.

show abstract

Section: Modeling Bti-induced Cmos Device Agingmentioning

confidence: 99%

Optimally Fortifying Logic Reliability through Criticality Ranking

et al. 2015

View full text Add to dashboard Cite

show abstract

“…Based on the reaction-diffusion mechanism, real time NBTI model is developed in [21,22] shown in Table I.…”

Section: A Standby Time Aware Nbti Modelingmentioning

confidence: 99%

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

Wang

Chen

Wang

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

Self Cite

View full text Add to dashboard Cite

Abstract-1 As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concerns for circuit designers. Consequently, we have seen a lot of research efforts on NBTI analysis and mitigation techniques. On the other hand, reducing leakage power remains to be one of the major design goals. Both NBTI-induced circuit degradation and standby leakage power have a strong dependency on the input patterns of circuits. In this paper, we propose a co-simulation flow to study NBTI-induced circuit degradation and leakage power, taking into account the different behaviors between circuit active and standby time. Based on this flow, we evaluate the efficacy of Input Vector Control (IVC) technique on mitigating circuit aging and reducing standby leakage power with experiments on benchmark circuits that are implemented in 90nm, 65nm, and 45nm technology nodes. The IVC technique is proved to be effective to mitigate NBTI-induced circuit degradation, saving up to 56% circuit performance degradation at 65nm technology node, and on average 30% circuit performance degradation across different technology nodes. Meanwhile, IVC technique can save up to 18% of the worst case leakage power. Since leakage power and NBTI-induced circuit degradation have different dependencies on the input patterns, we propose to derive Pareto sets for designers to explore trade-offs between the life-time reliability and leakage power.

show abstract

“…Manifesting itself in a gradual manner, the impact of NBTI may take days and months to affect timing and circuit delay and thus fail the system. Recent research works have confirmed that NBTI is getting worse with further scaling starting from 90nm technology [1][2] [3].…”

Section: Introductionmentioning

confidence: 99%

“…It has been reported as accurate enough to monitor the NBTI introduced threshold voltage changes. The NBTI compact device model follows the similar style as reported in [3]. The stress model is derived as:…”

Section: Introductionmentioning

confidence: 99%

“…The above measures have provided robust designs for several technology generations ranging from 0.5 um to 0.10 um. However, as feature size continues to shrink reaching the nanometer scale, these techniques will no longer be sufficient in the nanometer regime [1][2] [3]. The extremely small device feature size makes process variation, particle-induced transient errors, and device stress much more challenging.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

NBTI aware workload balancing in multi-core systems

Sun

Kodi

Louri

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

View full text Add to dashboard Cite

Abstract-As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such as Negative Bias Temperature Instability (NBTI). Unless this problem is addressed, chip multi-processor (CMP) systems face low yields and short mean-time-to-failure (MTTF). This paper proposes a new design framework for multi-core system that includes device wear-out impact. Based on device fractional NBTI model, we propose a new NBTI aware system workload model, and develop new dynamic tile partition (DTP) algorithm to balance workload among active cores while relaxing stressed ones. Experimental results on 64 cores show that by allowing a small number of cores (around 10%)to relax in a short time period (10 second), the proposed methodology improves CMP system yield. We use the percentage of core failure to represent the yield improvement. The new strategy improves the core failure number by 20 %, and extend MTTF by 30% with little degradation in performance (less than 6%).

show abstract

Predictive Modeling of the NBTI Effect for Reliable Design

Cited by 347 publications

References 7 publications

Optimally Fortifying Logic Reliability through Criticality Ranking

Optimally Fortifying Logic Reliability through Criticality Ranking

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

NBTI aware workload balancing in multi-core systems

Contact Info

Product

Resources

About