NBTI aware workload balancing in multi-core systems

Abstract

Abstract-As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such as Negative Bias Temperature Instability (NBTI). Unless this problem is addressed, chip multi-processor (CMP) systems face low yields and short mean-time-to-failure (MTTF). This paper proposes a new design framework for multi-core system that includes device wear-out impact. Based on device fractional NBTI model, we propose a new NBTI aware system workload model, and develop new dynamic tile partition (DTP) algorithm to balance workload among active cores while relaxing stressed ones. Experimental results on 64 cores show that by allowing a small number of cores (around 10%)to relax in a short time period (10 second), the proposed methodology improves CMP system yield. We use the percentage of core failure to represent the yield improvement. The new strategy improves the core failure number by 20 %, and extend MTTF by 30% with little degradation in performance (less than 6%).

NBTI mitigation in microprocessor designs

“…The results of the RTL simulation are given in Table 2: for each functional unit of interest, the number of PMOS transistors and the number of PMOS transistors that are stressed (as an average over the input vector configurations) is reported. Notice that the statistics reported in Table 2 are slightly different than the 50% assumption made in [17], providing a more precise and accurate evaluation methodology.…”

“…For leakage power, this is in the order of 10% [23]. The authors in [18,17] on the other hand, exploit the recovery phase typical of the NBTI process in order to mitigate degradation. The authors address emerging multicore architectures, proposing a workload balancing scheme [17] that aims at alternating cores between full workload phases and recovery phases.…”

“…The authors in [18,17] on the other hand, exploit the recovery phase typical of the NBTI process in order to mitigate degradation. The authors address emerging multicore architectures, proposing a workload balancing scheme [17] that aims at alternating cores between full workload phases and recovery phases. The scheduling of stress and recovery phases is exploited through the concept of "workload capacity" [18], in which the impact of the degradation on the delay is computed at run-time; cores are associated to delay-driven performance metrics, used to rank the cores from their degradation status stand-point.…”

“…Predictive analytical models have been derived for instance in [17,4,13] and they address gate-level computation. The degradation estimated in this work is based on analytical models shown in [22] for the long-term degradation computation as a function of the gate-level duty-cycle, and reported in Equation 1.…”

Load Balancing Approaches: Recent Computing Trends

“…By collecting precise information about how frequently the process creates child processes and how long the child processes execute by system calls. Jin Sun, Avinash Kodi, Ahmed Louri, and Janet M. Wang proposes [13] a new design framework for multicore system that includes device wear-out impact. Based on device fractional NBTI model.…”