NBTI mitigation in microprocessor designs

Corbetta, Simone; Fornaciari, William

doi:10.1145/2206781.2206791

Cited by 12 publications

(4 citation statements)

References 23 publications

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“…T. Chantem et al [15] perform a solution for allocating and scheduling tasks on an MPSoC architecture to overcome the processor aging. S. Corbetta and W. Bornaciari [16] explore the impact of different instruction allocation policies on the processor aging.…”

Section: Related Work A)mentioning

confidence: 99%

The Impact of Parallel Programming Interfaces on the Aging of a Multicore Embedded Processor

Vieira

Souza

Marques

et al. 2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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In order to meet the increasing performance demand of applications, the amount of cores in a single chip package has been increasing. However, the heat has been rising at a higher scale, which accelerates the aging process in modern processors. Therefore, wisely balancing the use of resources is important to extend its longevity. Frequency performance stagnates after a certain amount of concurrent threads starts executing. In such cases, the only result is a temperature rise that directly influences the aging process, reducing the processor lifetime. This unbalance between threads can be originated from many factors, which includes the way threads communicate and synchronize. Considering that those characteristics are related to the Parallel Programming Interface (PPI) used to parallelize the application, this work proposes to evaluate three widely used PPIs executing on an embedded multicore. We show that, depending on the characteristic of the application, by only switching from one PPI to another, it is possible to reduce the effects of aging. For that, we have developed a model based on the Arrhenius equation. We show that OpenMP has a lower impact on the processor aging for memory-bound applications: up to 38% and 68% lower than PThreads and MPI, respectively. On the other hand, PThreads presents the lowest impact on the processor aging for CPU-bound applications.

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Section: Related Work A)mentioning

confidence: 99%

The Impact of Parallel Programming Interfaces on the Aging of a Multicore Embedded Processor

Vieira

Souza

Marques

et al. 2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Increasing the idle ratio of the functional units of a processor to decrease NBTI effects is also considered in Corbetta and Fornaciari [2012] and Oboril et al [2012]. The former presents an instruction allocation strategy and the latter proposes a scheduling scheme to increase the idle ratio of timing-critical components.…”

Section: Architecture-level Nbti Effect Mitigation Techniquesmentioning

confidence: 99%

Magic

Karimi

Kanuparthi

Wang

et al. 2015

ACM Trans. Archit. Code Optim.

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The performance of an IC degrades over its lifetime, ultimately resulting in IC failure. In this article, we present a hardware attack (called MAGIC) to maliciously accelerate NBTI aging effects in cores. In this attack, we identify the input patterns that maliciously age the pipestages of a core. We then craft a program that generates these patterns at the inputs of the targeted pipestage. We demonstrate the MAGIC-based attack on the OpenSPARC processor. Executing this program dramatically accelerates the aging process and degrades the processor's performance by 10.92% in 1 month, bypassing existing aging mitigation and timing-error correction schemes. We also present two low-cost techniques to thwart the proposed attack.

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“…Furthermore, we have added a reliability library to the performance simulator, to dynamically measure the NBTI stress at architectural block level as instructions are executed, such that to provide thermal and reliability directed dynamic instruction scheduling strategies. The NBTI library is based on an off-line characterization of a MIPS-like RTL processor design, as previously done in [20].…”

Section: A Cycle-accurate Simulationmentioning

confidence: 99%

A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures

Corbetta

Zoni

Fornaciari

2012

2012 IEEE Computer Society Annual Symposium on VLSI

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Abstract-The increasing complexity of multi-core architectures demands for a comprehensive evaluation of different solutions and alternatives at every stage of the design process, considering different aspects at the same time. Simulation frameworks are attractive tools to fulfil this requirement, due to their flexibility. Nevertheless, state-of-theart simulation frameworks lack a joint analysis of power, performance, temperature profile and reliability projection at system-level, focusing only on a specific aspect. This paper presents a comprehensive estimation framework that jointly exploits these design metrics at system-level, considering processing cores, interconnect design and storage elements. We describe the framework in details, and provide a set of experiments that highlight its capability and flexibility, focusing on temperature and reliability analysis of multi-core architectures supported by Network-on-Chip interconnect.

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NBTI mitigation in microprocessor designs

Cited by 12 publications

References 23 publications

The Impact of Parallel Programming Interfaces on the Aging of a Multicore Embedded Processor

The Impact of Parallel Programming Interfaces on the Aging of a Multicore Embedded Processor

Magic

A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures

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