Prediction of delays induced by in-band RFI in CMOS inverters

Laurin, Jean‐Jacques; Zaky, S.G.; Balmain, K. G.

doi:10.1109/15.385879

Cited by 13 publications

(5 citation statements)

References 8 publications

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“…At the higher frequencies, we see less induced jitter and higher immunity, an effect not predicted by the simple theory. This variation of jitter with frequency was also noted by Laurin et al [2].…”

Section: Measurementssupporting

confidence: 83%

“…The simple theory predicts a symmetrical distribution of timing delays, and a maximum change in delay of . Equating the two times, and substituting (2) gives (6) Interestingly, this predicts that the immunity of the circuit will be independent of all switching parameters except for the logic threshold.…”

Section: A Immunity Level Of 'Xor' Circuitmentioning

confidence: 99%

“…E LECTROMAGNETIC interference (EMI) can cause random variations in the timing of digital circuits. This effect is known as EMI-induced jitter, and can occur at threat levels that are too low to lead to false switching [1], [2]. It is observed at all levels of integration up to very-large-scale-integration (VLSI) circuits [3].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A simple model of emi-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance

Robinson

Fischer²,

Flintoft

et al. 2003

IEEE Trans. Electromagn. Compat.

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Section: Measurementssupporting

confidence: 83%

Section: A Immunity Level Of 'Xor' Circuitmentioning

confidence: 99%

See 1 more Smart Citation

A simple model of emi-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance

Robinson

Fischer²,

Flintoft

et al. 2003

IEEE Trans. Electromagn. Compat.

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“…1) Effect of RFI on Circuits: EMI has various effects on circuits that exhibit different sensitivity levels. The effects of EM wave coupling to PCB traces and the consequences of this coupling on simple circuits were analyzed by Laurin et al [58]. With field strengths as high as 200 V/m, no disturbance was observed on the component.…”

Section: Research Studies Related To Susceptibility Of Ics To Emi (1996-2009)mentioning

confidence: 99%

The Electromagnetic Compatibility of Integrated Circuits—Past, Present, and Future

Ramdani

Sicard

Boyer

et al. 2009

IEEE Trans. Electromagn. Compat.

272

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Throughout the decades of continuous advances in semiconductor technology, from the discrete devices of the late 1950s to today's billon-transistor system-on-chip, there have always been concerns about the ability of components to operate safely in an increasingly disruptive electromagnetic environment. This paper provides a nonexhaustive review of the research work conducted in the field of electromagnetic compatibility (EMC) at the IC level over the past 40 years. It also brings together a collection of information and trends in IC technology, in order to build a tentative roadmap for the EMC of ICs until the year 2020, with a focus on measurement methods and modeling approaches.

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“…Various studies concerning malfunctions of digital circuits due to noise applied on signaling systems have been done. Some reports discuss the occurrence of malfunctions based on noise level and threshold level relationships [2,3], and others discuss the occurrence of malfunctions due to discrepancies in the timing with which signals are generated because of applied noise [4][5][6][7]. For malfunctions due to noise applied on power supply systems, there have been reports that have only shown the results of measuring frequency characteristics of malfunction levels that occur when sine wave noise was added to various types of logic ICs [8,9].…”

Section: Introductionmentioning

confidence: 98%

An analysis on malfunction of a flip‐flop due to impulsive noise on power supply

Tsukagoshi

Nitta

Mutoh

2003

Electron Comm Jpn Pt II

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SUMMARYTo dynamically analyze the output inversion mechanism due to impulsive noise applied on a DC power supply Vcc, assuming that a flip-flop consisting of two transistors is used as the power supply noise sensor, the authors propose a simple circuit model not based on a nonlinear transistor model and a simple inversion model for performing a voltage comparison between the output pin Vc 1 [see Fig. 1(a)] and the applied voltage Vin of the power supply to determine whether or not inversion occurred. They also propose a technique for estimating noise immunity from transient response characteristics of the flip-flop, which were obtained by using these models, and compare the estimated values obtained according to this technique with simulation values using SPICE and experimental values to verify the validity of this model within a range limited by the time constant Tc of the simple circuit model [consisting of Rc 1 , R 12 , and C 1 in Fig. 1(d)] and the overdriving factor (ODF) of the transistors. The results clearly indicated that the time constant Tc of the simple circuit model produced a response delay for output pin Vc 1 relative to the applied voltage Vin of the power supply on which the impulsive noise was applied, that an inverted potential gradient for which Vc 1 > Vin was temporarily generated with the power supply voltage when the power supply voltage dropped, that this caused the current to flow backwards to the power supply side, and that making the base current of the transistor go in the negative direction is the cause of the output inversion.

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Prediction of delays induced by in-band RFI in CMOS inverters

Cited by 13 publications

References 8 publications

A simple model of emi-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance

A simple model of emi-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance

The Electromagnetic Compatibility of Integrated Circuits—Past, Present, and Future

An analysis on malfunction of a flip‐flop due to impulsive noise on power supply

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