Practical Determination of Individual Element Resistive States in Selectorless RRAM Arrays

Abstract

Abstract-Three distinct methods of reading multi-level crosspoint resistive states from selector-less RRAM arrays are implemented in a physical system and compared for read-out accuracy. They are: the standard, direct measurement method and two methods that attempt to enhance accuracy by computing cross-point resistance on the basis of multiple measurements. Results indicate that the standard method performs as well as or better than its competitors. SPICE simulations are then performed with controlled amounts of non-idealities introduced in the system in order to test whether any technique offers particular resilience against typical practical imperfections such as crossbar line resistance. We conclude that even though certain non-idealities are shown to be minimised by different circuit-level read-out strategies, line resistance within the crossbar remains an outstanding challenge.

An FPGA-Based Instrument for En-Masse RRAM Characterization With ns Pulsing Resolution

“…Test array configuration and measured read-out errors are shown in Fig.6. Typical crossbar parasitic-induced read-out error patterns can be observed, similar to those described in [18]. These include: a) overestimates due to non-zero access framework resistance …”

“…b) Transitioning the array handler to a trans-resistance amplifierbased read-out scheme [18] so that precise, direct control over the bias voltage across the DUT is maintained at all times, including during on-board oscilloscope operation. With these upgrades we intend to further enhance read-out accuracy.…”

“…The write scheme is the standard 'V write /2' method [10], as in Fig. 2(b) that offers a good compromise between reducing unwanted cross-programming and restricting write operation power dissipation [18]: Gain 1/2 amplifiers act as a cross-talk protection mechanism by ensuring that the bit-and word-complement devices are not subjected to more than half the voltage applied to the DUT during the write operation. Simultaneously, the voltage drop across R r remains close to zero.…”

“…Although the effects of such circuit imperfections have been studied extensively through simulation and experiment [9], [15], [18], the role of inaccuracies in capturing voltage values (in this case at V bias and V src ) due to imperfect data converters is still unknown.…”

Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges

“…The widely used V w /2 and V w /3 writing schemes [4], [5], [21], [26] suffer from this spurious selection and expose cells to possible non-desired state alterations [22]. At the same time, this partial selection produces a leakage phenomena that should be addressed [27], [28]. More in depth information about how this stress affects data retention can be found in [12], [29], [30].…”