Practical Asynchronous Interconnect Network Design

Quinton, B.R.; Greenstreet, Mark R.; Wilton, Steven J. E.

doi:10.1109/tvlsi.2008.917545

Cited by 16 publications

(4 citation statements)

References 16 publications

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“…This is in contrast to techniques that utilize synchronous tools for implementing a specific network [4]. In this work, we give an overview of our circuits and design automation techniques, and compare the resulting asynchronous NoC to a synchronous one generated by an existing tool.…”

Section: Introductionmentioning

confidence: 99%

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Gebhardt

You

Stevens

2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

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Abstract-Power consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous networkon-chip implementations, optimized for a number of SoC designs. We adapted the COSI-2.0 framework with ORION 2.0 router and wire models for synchronous network generation. Our own tool, ANetGen, specifies the asynchronous network by determining the topology with simulated-annealing and router locations with force-directed placement. It uses energy and delay models from our 65 nm bundled-data router design. SystemC simulations varied traffic burstiness using the self-similar b-model. Results show that the asynchronous network provided lower median and maximum message latency, especially under bursty traffic, and used far less router energy with a slight overhead for the interrouter wires.

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Section: Introductionmentioning

confidence: 99%

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Gebhardt

You

Stevens

2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

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“…This difference accounts for the specificities of the KeyRing protocol. It is worth noting that similar circuits were independently proposed by Traylor in [27] and Quinton in [28].…”

Section: Keyring Microarchitecturementioning

confidence: 99%

Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow

Fiorentino

Thibeault

Savaria

2021

IET Computers & Digital Tech

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A self-timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing-driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low-power self-timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing-driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing-driven synthesis and static timing analysis. Finally, two 32-bit RISC-V processors are presented; called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock-gating and SynV without clock-gating.

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“…We will later introduce a number of generalizations of this circuit (with multiple inputs, outputs and state variables) that are not covered by this publication. A dual-rail version of this circuit has also been used in asynchronous interconnect design [8], [9]. This version also uses flip-flops as state-holding elements but requires more XOR gates in the control logic.…”

Section: A Simple Pipeline Stagementioning

confidence: 99%

Click Elements: An Implementation Style for Data-Driven Compilation

Peeters

Beest

Wit

et al. 2010

2010 IEEE Symposium on Asynchronous Circuits and Systems

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This paper presents a new design template and design flow for the implementation of data-driven asynchronous circuits. It relies on the use of edge-triggered flip-flops as the only storage elements, not only for the datapaths, but also for the control circuits; latches and C-elements that are common in many asynchronous circuit design styles are not required. The design template uses a two-phase handshake protocol for inter-component communication. In a pipeline structure, these circuits operate near the speed of Mousetrap circuits, but the required design-flow is simpler. The implementation stylewhich we refer to as Click elements -has been chosen to resemble synchronous circuits as much as possible. This allows for the use of conventional optimization and timing tools in the design flow and for a cheaper design-for-test implementation. The click templates are well suited for a data-flow driven compilation flow, which avoids much of the control overhead of traditional syntax-directed compilation. The two-phase circuits show a significant improvement in performance and energy efficiency compared to four-phase single-rail circuits.

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Practical Asynchronous Interconnect Network Design

Cited by 16 publications

References 16 publications

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow

Click Elements: An Implementation Style for Data-Driven Compilation

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