Click Elements: An Implementation Style for Data-Driven Compilation

Abstract

This paper presents a new design template and design flow for the implementation of data-driven asynchronous circuits. It relies on the use of edge-triggered flip-flops as the only storage elements, not only for the datapaths, but also for the control circuits; latches and C-elements that are common in many asynchronous circuit design styles are not required. The design template uses a two-phase handshake protocol for inter-component communication. In a pipeline structure, these circuits operate near the speed of Mousetrap circuits, but the required design-flow is simpler. The implementation stylewhich we refer to as Click elements -has been chosen to resemble synchronous circuits as much as possible. This allows for the use of conventional optimization and timing tools in the design flow and for a cheaper design-for-test implementation. The click templates are well suited for a data-flow driven compilation flow, which avoids much of the control overhead of traditional syntax-directed compilation. The two-phase circuits show a significant improvement in performance and energy efficiency compared to four-phase single-rail circuits.

A Clustered GALS NoC Architecture with Communication-Aware Mapping

“…Many asynchronous pipelined links are available in literature; however, all of them suffer from incompatibility with EDA tools. Exploiting click-element [14] facilitates keeping our performance goals, and, moreover, enables support of use of standard cells in our design.…”

“…Using non-standard elements, like Muller element, in asynchronous circuit design usually leads use of a customized library for synthesis. To resolve this issue, we use a fully standard cell compatible structure: a Clickelement [14]. We designed the Muller elements of the design using click structure.…”

A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline

“…The datapath uses a bundled data encoding [2] and the control is based on the Click elements two-phase protocol [4]. Click controllers keep track of the current state (phase) of each pipeline stage using toggle flip-flops.…”

“…This paper introduces a new self-timed pipeline developed for an L1 instruction cache. The pipeline integrates features from Octasic's token-based architecture and Click elements [4]. Simulation and post-layout timing were performed using a 28nm bulk process.…”

Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA

“…The community has attempted to address performance issues by improving the control flow [6], [7], [8]. Recently, Teak [9] and Click [10] have been proposed as dataflow synthesis frameworks to tackle the control overhead of Balsa and Haste, respectively.…”