A deeply pipelined and parallel LDPC decoder architecture is proposed in this paper. The main feature of this architecture is the ∆-update scheme, which relaxes the data dependency requirement and allows for deeper pipelines than typical decoders. The proposed architecture also has the flexibility to handle a large number of codes. Frame error rate performance is shown for three codes with different quantization parameters. Finally, the impact of pipeline depth on processing time and on the energy-delay product (EDP) is evaluated from post-synthesis results. The results show that the ability to have deeper pipelines can lead to large reductions in EDP.
The conventional synchronous design approach is not suitable for implementing self-timed circuits on FPGAs. When design tools try to meet synchronous circuits timing constraints, they can violate self-timed setup timing constraints. This paper proposes a new methodology for implementing self-timed circuits in modern FPGAs using the Xilinx Hierarchical Design flow and a convenient architecture of a configurable delay element. Reported simulation results, in accordance with static timing analysis, show that the self-timed timing constraints are satisfied using our design methodology.
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