A practical design method for prototyping self-timed processors using FPGAs

Fiorentino, Mickael; Savaria, Yvon; Thibeault, Claude; Gervais, Pascal

doi:10.1109/iscas.2016.7538907

Cited by 4 publications

(2 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The works reported in Ref. [37,40] explore the idea further by defining generated clocks, derived from virtual clocks, to model the propagation of events in the control path. The resulting timing paths are defined as zerocycle paths to account for the non-periodic characteristics of BD operations.…”

Section: Timing Analysismentioning

confidence: 99%

“…(ii) Desynchronization design flow [36], which starts with the synthesis of a synchronous specification and converts the netlist into an equivalent asynchronous BD circuit (flip-flops are replaced with latches, and the clock tree is replaced with handshake control networks). (iii) Template-based approach [37,38], which relies on various empirical techniques applied to standard synthesis tools to synthesize hardware descriptions of BD circuits. Control structures (asynchronous templates) are designed at the gate level, and a set of dont_touch directives are used to prevent their automatic removal.…”

Section: Logical Synthesismentioning

confidence: 99%

See 1 more Smart Citation

Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow

Fiorentino

Thibeault

Savaria

2021

IET Computers & Digital Tech

Self Cite

View full text Add to dashboard Cite

A self-timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing-driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low-power self-timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing-driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing-driven synthesis and static timing analysis. Finally, two 32-bit RISC-V processors are presented; called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock-gating and SynV without clock-gating.

show abstract

Section: Timing Analysismentioning

confidence: 99%

Section: Logical Synthesismentioning

confidence: 99%

Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow

Fiorentino

Thibeault

Savaria

2021

IET Computers & Digital Tech

Self Cite

View full text Add to dashboard Cite

show abstract

Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out

et al. 2019

View full text Add to dashboard Cite

Proceeding miniaturization in the VLSI circuits continues to pose challenges to the conventionally used synchronous design style in microprocessors. These include the distribution of clock in the GHz range, robustness to delay variations, reduction in electromagnetic interference, and energy conservation, to name a few. The asynchronous logic has been known for its ability to address the aforementioned challenges by means of the closed-loop handshake protocols, instead of notorious clock signals. Because of these advantages, there have been numerous attempts on building general and special purpose microprocessors during the last three decades. Still, however, the number of asynchronous processors commercially available is scarce, mainly due to an insufficient electronic design and automation tools support, an ambiguous design flow and testing mechanisms for asynchronous logic and, most importantly, absence of a forum to look for relevant works, explaining the design steps and tools for such microprocessors. This paper is intended to bridge this gap by 1) reviewing the design principles of asynchronous logic, including classification, signaling conventions, and pipelining approaches; 2) presenting the complete design flow and available electronic design and automation tools; 3) developing an encyclopedia of various general and special purpose microprocessors proposed by far; and 4) presenting an evaluation of those works in terms of area on the die and performance metrics. This paper will also serve as guidelines for the asynchronous microprocessor design and implementation in all phases from specification to tape-out.INDEX TERMS Asynchronous logic, electronic design and automation, microprocessor.

show abstract