Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out

Abstract

Proceeding miniaturization in the VLSI circuits continues to pose challenges to the conventionally used synchronous design style in microprocessors. These include the distribution of clock in the GHz range, robustness to delay variations, reduction in electromagnetic interference, and energy conservation, to name a few. The asynchronous logic has been known for its ability to address the aforementioned challenges by means of the closed-loop handshake protocols, instead of notorious clock signals. Because of these advantages, there have been numerous attempts on building general and special purpose microprocessors during the last three decades. Still, however, the number of asynchronous processors commercially available is scarce, mainly due to an insufficient electronic design and automation tools support, an ambiguous design flow and testing mechanisms for asynchronous logic and, most importantly, absence of a forum to look for relevant works, explaining the design steps and tools for such microprocessors. This paper is intended to bridge this gap by 1) reviewing the design principles of asynchronous logic, including classification, signaling conventions, and pipelining approaches; 2) presenting the complete design flow and available electronic design and automation tools; 3) developing an encyclopedia of various general and special purpose microprocessors proposed by far; and 4) presenting an evaluation of those works in terms of area on the die and performance metrics. This paper will also serve as guidelines for the asynchronous microprocessor design and implementation in all phases from specification to tape-out.INDEX TERMS Asynchronous logic, electronic design and automation, microprocessor.

An FPGA Compliant Single-Rail Encoded Asynchronous Pipeline

“…Down-scaling of semiconductor technology increases the number of transistors exponentially, allowing integration of higher density Systems on Chip (SOC) to build larger circuits [1]. The interconnect delays have become so significant that it is challenging to distribute the clock network over the chip area without ignoring clock skews [2]. The high power and clock skew associated with distributed networks compels researchers to consider asynchronous design methodologies [3].…”

“…The path connecting two stages in an asynchronous pipeline can either be a single-rail or dual-rail bit encoded. In a single-rail bit encoding, one wire represents a single bit [2], whereas a dual-rail encoding requires two wires to represent a single bit. Both datapaths require handshake protocols [7], either two-phase or four-phase [8] [9], comprising Request (Req) and Acknowledge (Ack) signals, to synchronize various stages.…”

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

“…The process completion time between two synchronous logic blocks is evaluated based on their critical paths, and the clock period for the design must be larger than the worst of these critical paths, hence limiting the scope of speed improvement. Clock skew and hence clock delay balancing are difficult to manage due to technology scaling, as the clock signal needs to arrive at the same time at all storage elements [46][47][48][49]. Moreover, synchronous circuits invest 40% and more of its power in clock distribution [50,51], and as the design grows in complexity, additional delay units are required to tune the delay from the clock source to the flip-flops/latches to overcome clock skew [52][53][54].…”

“…This implies that the presence of a global clock signal leads to more latency and power consumption. Asynchronous circuits provide an alternate solution for these challenges that arise due to the presence of a global clock [49,55], as the clock signal is replaced by the handshaking (request REQ and acknowledge ACK) signals in such circuits. The datapath becomes active upon the reception of a request signal REQ, and it goes back to the inactive state after it has completed its operation and issued an acknowledge signal ACK.…”

“…The involvement of technology in our day to day life, however, creates the need for even faster and more compact electronic devices with lower power consumption. The technology scaling imposes various limitations on synchronous circuits [49,[57][58][59], and the asynchronous design approach is being reconsidered by various researchers to overcome the limitations due to the presence of the clock signal. The demand for portable electronic devices with minimal power consumption [60] without compromising the processing speed and silicon area is another major concern [61,62].…”