Power and Energy Normalized Speedup Models for Heterogeneous Many Core Computing

Al-hayanni, Mohammed A. Noaman; Rafiev, Ashur; Shafik, Rishad; Xia, Fei

doi:10.1109/acsd.2016.16

Cited by 7 publications

(21 citation statements)

References 17 publications

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“…Parallelization factor is the fraction of the workload executed in parallel; = 1 is the ideal scaling case. The law is famous for predicting that even a small drop in causes the throughput to quickly saturate [3]. Gustafson's model argues, however, that it is possible to scale the speedup linearly if the workload size can be increased with the number of cores, increasing the parallelizable portion while keeping the sequential portion the same [3].…”

Section: Non-ideal Scaling and Heterogeneitymentioning

confidence: 99%

“…There are a number of known models for ( ) [3], shown in Figure 4. Amdahl's Law computes the speed-up with k cores assuming a fixed-size workload.…”

Section: Non-ideal Scaling and Heterogeneitymentioning

confidence: 99%

“…The law is famous for predicting that even a small drop in causes the throughput to quickly saturate [3]. Gustafson's model argues, however, that it is possible to scale the speedup linearly if the workload size can be increased with the number of cores, increasing the parallelizable portion while keeping the sequential portion the same [3]. Sun and Ni expand this idea towards a general metric ( ), showing how the memory requirement of an algorithm scales relative to the computation requirement, and confirm that for ( ) ≥ it is possible to achieve linear or better-than-linear many-core scaling [3].…”

Section: Non-ideal Scaling and Heterogeneitymentioning

confidence: 99%

“…A major challenge for the precise analysis of the effectiveness of using parallelization for these goals is to determine the parallelizability of any particular execution, which is related to complex issues such as software and hardware architecture details and must be modelled on a per-execution basis [3]. Another challenge is that quantitative studies of power and/or throughput improvements for any DVFS decision need complicated executiondependent models [4].…”

Section: Introductionmentioning

confidence: 99%

“…The scheme of dynamic voltage and frequency scaling (DVFS) scales and clock frequency (henceforth called ) together in order to obtain the best throughput under a given power budget or to save power for a given throughput requirement [1]. 3 The reliable operating region Operational reliability depends on the system platform including various hardware-related design-time and runtime decisions as well as applications and their requirements. Different metrics can be used to describe the degree of reliability.…”

Section: Introductionmentioning

confidence: 99%

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Voltage, Throughput, Power, Reliability, and Multicore Scaling

et al. 2017

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ARM 1 AbstractParallelization has been used to maintain a reasonable balance between energy consumption and performance in computing platforms especially in modern multi-and many-core systems. This paper studies the interplay between performance and energy, and their relationships with parallelization scaling in the context of the reliable operating region, focusing on the effectiveness of parallelization scaling in throughput-power tradeoffs. Theoretical and experimental explorations show that a meaningful cross-platform analysis of this interplay can be achieved using the proposed method of binormalization of the ROR. The concept of this interplay is captured in an online tool for finding optimal operating points. IntroductionIn digital CMOS circuits, a higher supply voltage (called henceforth) usually permits a higher operating (clock) frequency for capacitive load-balancing, and hence a higher throughput, given the same hardware platform. The scheme of dynamic voltage and frequency scaling (DVFS) scales and clock frequency (henceforth called ) together in order to obtain the best throughput under a given power budget or to save power for a given throughput requirement [1].It is possible to increase system throughput for a given power limit, or to reduce power whilst maintaining throughput, by combining DVFS with parallelization or scaling to multiple computation units if the computation can be parallelized [2]. A major challenge for the precise analysis of the effectiveness of using parallelization for these goals is to determine the parallelizability of any particular execution, which is related to complex issues such as software and hardware architecture details and must be modelled on a per-execution basis [3]. Another challenge is that quantitative studies of power and/or throughput improvements for any DVFS decision need complicated executiondependent models [4]. This paper explores the interplay between DVFS and parallelization scalability with respect to performance and power. The interplay is captured using the concept of a reliable operating region (ROR), which can be established from the knowledge of system reliability through experiments or simulations. The ROR therefore provides containment for platform and application specifics, hence helping to make the further analysis steps generic.The focus of this paper is the effectiveness of parallelization scaling, the latter denoted as .The ROR-based method can explore across the entire voltage range of a platform, from subthreshold to super-threshold regions. The explorations and models presented in this paper confirm and explain the general view that combined DVFS and parallelization scaling produces the best advantage when is scaled down to near-threshold voltages. This is known as near-threshold

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Section: Non-ideal Scaling and Heterogeneitymentioning

confidence: 99%

“…There are a number of known models for ( ) [3], shown in Figure 4. Amdahl's Law computes the speed-up with k cores assuming a fixed-size workload.…”

Section: Non-ideal Scaling and Heterogeneitymentioning

confidence: 99%

Section: Non-ideal Scaling and Heterogeneitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Voltage, Throughput, Power, Reliability, and Multicore Scaling

et al. 2017

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A Novel Speedup Evaluation for Multicore Architecture Based Topology of On-Chip Memory

Wang

Shi

Zhang

2020

Parallel Architectures, Algorithms and Programming

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Amdahl's law in the context of heterogeneous many‐core systems – a survey

Al-hayanni

Xia

Rafiev

et al. 2020

IET Computers & Digital Techniques

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For over 50 years, Amdahl's Law has been the hallmark model for reasoning about performance bounds for homogeneous parallel computing resources. As heterogeneous, many-core parallel resources continue to permeate into the modern server and embedded domains, there has been growing interest in promulgating realistic extensions and assumptions in keeping with newer use cases. This study aims to provide a comprehensive review of the purviews and insights provided by the extensive body of work related to Amdahl's law to date, focusing on computation speedup. The authors show that a significant portion of these studies has looked into analysing the scalability of the model considering both workload and system heterogeneity in real-world applications. The focus has been to improve the definition and semantic power of the two key parameters in the original model: the parallel fraction (f) and the computation capability improvement index (n). More recently, researchers have shown normal-form and multi-fraction extensions that can account for wider ranges of heterogeneity, validated on many-core systems running realistic workloads. Speedup models from Amdahl's law onwards have seen a wide range of uses, such as the optimisation of system execution, and these uses are even more important with the advent of the heterogeneous many-core era.

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Power and Energy Normalized Speedup Models for Heterogeneous Many Core Computing

Cited by 7 publications

References 17 publications

Voltage, Throughput, Power, Reliability, and Multicore Scaling

Voltage, Throughput, Power, Reliability, and Multicore Scaling

A Novel Speedup Evaluation for Multicore Architecture Based Topology of On-Chip Memory

Amdahl's law in the context of heterogeneous many‐core systems – a survey

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