Voltage, Throughput, Power, Reliability, and Multicore Scaling

Abstract

ARM 1 AbstractParallelization has been used to maintain a reasonable balance between energy consumption and performance in computing platforms especially in modern multi-and many-core systems. This paper studies the interplay between performance and energy, and their relationships with parallelization scaling in the context of the reliable operating region, focusing on the effectiveness of parallelization scaling in throughput-power tradeoffs. Theoretical and experimental explorations show that a meaningful cross-platform analysis of this interplay can be achieved using the proposed method of binormalization of the ROR. The concept of this interplay is captured in an online tool for finding optimal operating points. IntroductionIn digital CMOS circuits, a higher supply voltage (called henceforth) usually permits a higher operating (clock) frequency for capacitive load-balancing, and hence a higher throughput, given the same hardware platform. The scheme of dynamic voltage and frequency scaling (DVFS) scales and clock frequency (henceforth called ) together in order to obtain the best throughput under a given power budget or to save power for a given throughput requirement [1].It is possible to increase system throughput for a given power limit, or to reduce power whilst maintaining throughput, by combining DVFS with parallelization or scaling to multiple computation units if the computation can be parallelized [2]. A major challenge for the precise analysis of the effectiveness of using parallelization for these goals is to determine the parallelizability of any particular execution, which is related to complex issues such as software and hardware architecture details and must be modelled on a per-execution basis [3]. Another challenge is that quantitative studies of power and/or throughput improvements for any DVFS decision need complicated executiondependent models [4]. This paper explores the interplay between DVFS and parallelization scalability with respect to performance and power. The interplay is captured using the concept of a reliable operating region (ROR), which can be established from the knowledge of system reliability through experiments or simulations. The ROR therefore provides containment for platform and application specifics, hence helping to make the further analysis steps generic.The focus of this paper is the effectiveness of parallelization scaling, the latter denoted as .The ROR-based method can explore across the entire voltage range of a platform, from subthreshold to super-threshold regions. The explorations and models presented in this paper confirm and explain the general view that combined DVFS and parallelization scaling produces the best advantage when is scaled down to near-threshold voltages. This is known as near-threshold

Amdahl's law in the context of heterogeneous many‐core systems – a survey

“…It can be verified that (29) transforms into Sun-Ni's model (10) by substituting f 1 with 1 − f and f n with f ⋅ g(n), and f j = 0, ∀1 < j < n. For g(n) = n the model further transforms into Gustafson's (7), and for g(n) = 1 it becomes classical Amdahl's law (4). Other related models, for instance that extending models similar to Sun-Ni's over Hill-Marty asymmetric heterogeneity [55], are also covered by the multi-fraction model with similar arguments.…”

“…The classical method for modelling the speedup of workload processing caused by some measure of improving the computation capabilities is known as Amdahl's law, which developed from observations presented by Amdahl in 1967 [1]. Amdahl [2,42] no p-fraction yes no no no no [3] no p-fraction yes yes yes yes no [5] load balancing and scheduling p-fraction yes yes yes yes no [7] no p-fraction yes yes yes no no [13] no parallelism yes yes no no no [14] load balancing and scheduling parallelism yes yes no no no [15] no p-fraction yes yes yes yes no [17] synchronisation and communication p-fraction yes yes no no no [18] no p-fraction yes no no no no [4,43] no p-fraction yes no no no no [19,20,44] no p-fraction yes no no no no [22] no p-fraction yes no no no no [24] no multi p-fraction and parallelism yes yes no no no [25] no p-fraction yes no no no no [26] time of parallel tasks no no no no no no [27] no p-fraction yes no no no no [28] no p-fraction yes no no no no [29] no no yes yes no no no [38] no [68] no p-fraction yes no no no no [69] run-time no no yes no no yes [70] run-time no no yes yes yes yes provide a mathematical formula for this law, which was later formulated based on his verbal arguments. Given the context of this paper, which is about the parallelisation of workloads on M/MCP systems, 'improvement of computation capabilities' generally means the incorporation of multiple processing units (to be called 'cores' in this paper) to improve the speed of workload execution, unless otherwise noted.…”

“… Speedup versus the number of cores for (a) Amdahl's law, (b) Gustafson's model, (c) Sun–Ni's model with . Figure adapted from [7]…”

“…On performance, it is well known that the parallelisation of workloads may bring speedup [1][2][3][4][5]. On energy efficiency, with the advent of such hardware techniques as dynamic voltage and frequency scaling (DVFS), it is possible to trade an increase in the number of processing units for a reduction of energy consumption without affecting performance [6][7][8][9].…”

PARMA: Parallelization-Aware Run-Time Management for Energy-Efficient Many-Core Systems

“…Run-time management is a set of methods for managing hardware/software knobs and monitors under variable workloads to improve system operation, for example by optimizing some chosen metric in the performance/energy trade-off [7]. Existing run-time algorithms react to workload change by dynamically scaling voltage/frequency (DVFS) [8], in combination with task mapping and core allocations [9].…”