Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

Faynot, O.; Andrieu, F.; Weber, O.; Fenouillet-Béranger, C.; Perreau, P.; Mazurier, J.; Benoist, T.; Rozeau, O.; Poiroux, T.; Vinet, M.; Grenouillet, L.; Noël, J.‐P.; Possémé, N.; Barnola, S.; Martin, F.; Lapeyre, C.; Cassé, M.; Garros, X.; Jaud, M.-A.; Thomas, Olivier; Cibrario, G.; Tosti, L.; Brévard, L.; Tabone, C.; Gaud, P.; Barraud, S.; Ernst, T.; Deleonibus, S.

doi:10.1109/iedm.2010.5703287

Cited by 71 publications

(29 citation statements)

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“…Thus, the thicker the buried oxide, the higher the source to drain coupling will be. Scaling down of the buried oxide is mandatory to maintain the electrostatic characteristics of MOSFETs (Figure 6(a)) [25][26][27][28]. Recent results have shown that [29,30]; (b) strained dual channel CMOS process flow [29].…”

Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 95%

“…This could allow for large scale integration for state-of-the-art systems-on-a-chip (SOC) [25,26]. A very important figure of merit that emphasizes SOI advantages over bulk technology is shown in Figure 6(b) [27]; for a given propagation delay time, ring oscillators demonstrate lower dynamic powers, P dyn , than bulk technology. This has been shown [18] for several nodes already, including the sub-20-nm node on FDSOI [27].…”

Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 98%

“…buried oxide could be scaled to 10 nm on large 300 mm diameter wafers with Si layers as thin as 6 nm [25][26][27][28]. The control of such substrates could lead to multi-threshold control.…”

Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 99%

“…A very important figure of merit that emphasizes SOI advantages over bulk technology is shown in Figure 6(b) [27]; for a given propagation delay time, ring oscillators demonstrate lower dynamic powers, P dyn , than bulk technology. This has been shown [18] for several nodes already, including the sub-20-nm node on FDSOI [27]. Moreover, it is possible to reduce delay time for a given P dyn xT p product.…”

Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 99%

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Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.The international technology roadmap of semiconductors (ITRS) [1] distinguishes three types of products: high performance (HP), low operating power (LOP) and low standby power (LSTP) devices. In the HP case, a landmark has been reached at the 32-nm node: the contribution from static power dissipation approaches the dynamic power contribution [2]. Multigate devices could improve this somewhat by increasing the saturation current to leakage current ratio.In this review, we will first analyze the primary limitations and showstoppers of CMOS scaling. Issues on gate stack, channel and source and drain engineering as well as new device architectures (FDSOI or multigate devices) are discussed.Low power consumption and heterogeneous function integration will be leveraged by future nomadic systems. The increased number of devices and different types of signals will, in turn, require the leveraging of 3D IN package or ON chip co-integration. Limitations, showstoppers and opportunities of Si CMOS scalingCMOS device engineering consists of minimizing leakage current and the maximization of output current. In sub-100-nm CMOS devices, non-stationary transport is more important than diffusive transport. To this end, several questions arise related to the origins of the leakage currents, non-stationary transport limitations and supply voltage scaling.

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Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 95%

Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 98%

Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 99%

Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 99%

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Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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“…Recently, in addition to shrinking technology node, there are many proposals of new structure transistors which enable further advancement of LSI performance beyond the limit of the scaling, and such transistors are also considered to be more suitable for the ultra-low voltage operation. Transistor called FD-SOI, ET-SOI, or SOTB [1,2] was proposed as one of the improved structures of conventional planer bulk MOSFET. In this structure, pMOS and nMOS which have ultra-low dose channels are shaped on the thin SOI layer.…”

Section: Introductionmentioning

confidence: 99%

Impacts of flexible <i>V<sub>th</sub></i> control, low process variability, and steep SS with low on-current of new structure transistors to ultra-low voltage designs

Ogasahara¹,

Nakagawa²,

Sekigawa³

et al. 2015

IEICE Electron. Express

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This paper discusses impacts of flexible V th control, low process variability, and steep SS with small on-current of new structure devices on ultra-low voltage circuits. Our simulation results based on PTM 22 nm model clarify applicability of ultra-low voltage operation to a nominal speed common SoC designs by an introduction of V th control as well as low power sensor nodes. We also reveal requirement of process variability suppression for high energy efficiency with steep SS transistors, and utilization of small on-current steep SS transistors to low power and low speed applications. Our qualitative discussion well explains these experiment results.

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