Abstract-This paper proposes an all-digital measurement circuit called a "gated oscillator" to capture the waveforms of dynamic power supply noise. An improved gated oscillator with a power-gating structure is also proposed. The gated oscillator is constructed using standard cells, and thus is easily embedded in SoCs. Its performance was evaluated using test chips fabricated in a 90 nm process. The gated oscillator achieved 5.3-5.9 Gsample/s with an area of 10.08 6.72 m 2 , and the improved power gating structure achieved 6.6-8.3 Gsample/s in a 90 nm process. The characteristics of the gated oscillator and related design issues are also discussed. These characteristics were verified on silicon. We evaluated the effect of the decoupling capacitance based on measurement results obtained using the gated oscillator, and demonstrated that it could be used to verify power integrity.
Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB
OPEN ACCESSJ. Low Power Electron. Appl. 2014, 4
189(silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed.Keywords: field programmable gate array (FPGA); static leakage power reduction; fine-grained body biasing; silicon on thin buried oxide (SOTB)
This paper demonstrates an implementation of physical unclonable function (PUF) using complementary organic transistors operating at low-voltage. PUF is an essential security element, and is important for various applications of organic devices. We implement a simple buskeeper PUF, which consists of two inverters. We confirm that the PUF bit values on the test chip can be read at a standard voltage for electronic circuits (3.3 V) via a standardized circuit board interface. We observed a low static current consumption (11.8 μA/90 bits) for the PUF chip. The PUF performance, chip-to-board interface performance, and requirements for the board interface in an organic transistor chip are discussed based on the measurement results of the test chip.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.