Placing, Routing, and Editing Virtual FPGAs

Abstract

Abstract. This paper presents the benefits of using a generic FPGA tool set developed at the university of Brest for programming virtual FPGA structures. From a high level FPGA description, the basic FPGA tools such a placer, a router or an editor are automatically generated. The FPGA description is not constrained by any model, so that abstract FPGA structures, such as virtual FPGAs, can directly exploit the tool set as their basic programming tools.

Model‐driven physical‐design automation for FPGAs: fast prototyping and legacy reuse

“…Amongst the numerous efforts in this direction, the Madeo project has overcome the performance challenges of object‐oriented languages in the context of FPGA design automation. It showed that dynamically typed languages can serve for creating high density logic designs , proposing the first virtual FPGA prototyping environment and proving that, harnessing the power of OO software design, one could create a flexible yet competitive EDA toolkit that even today enables breakthrough research in the field . Meanwhile, OO design became widely accepted by the EDA community through languages such as C++ (i.e., systemC ) and Java (i.e., JHDL ).…”

An efficient FPGA overlay for portable custom instruction set extensions

“…By implementing virtual LUTs directly into physical LUTs and by replacing routing multiplexers with LUTs in route through mode (see also Section III-B), a PV-ratio of 40x was achieved in [2]. As another way to reduce implementation cost, the authors of [3] restricted the routing freedom of the overlay interconnection network. For a prototype implementation of a linear systolic fine-grained overlay architecture, a PVratio of 16:1 was reported.…”