2013
DOI: 10.1002/spe.2190
|View full text |Cite
|
Sign up to set email alerts
|

Model‐driven physical‐design automation for FPGAs: fast prototyping and legacy reuse

Abstract: WOSInternational audienceRedesign of nontrivial software is often a challenge. Ciprian Teodorov et al. [4] addressed physical-design automation and presented a methodological approach relying on model-driven engineering. Also, they summarized some lessons learned from the incremental redesign of Madeo, a toolkit that targets field-programmable gate array design automation

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2014
2014
2023
2023

Publication Types

Select...
2
2

Relationship

1
3

Authors

Journals

citations
Cited by 4 publications
(2 citation statements)
references
References 51 publications
(46 reference statements)
0
1
0
Order By: Relevance
“…The MARTE standard [3] (Modeling and Analysis of Real-Time and Embedded Systems) offers a methodology for SoC co-design [4], with GASPARD [5] as the SoC co-design environment to move from high-level MARTE specifications to an executable platform. Teodorov [6] has demonstrated regression-free inheritance refactoring while offering additional debugging facilities, These works bring new functionalities (exploration, debugging, automatic generation), while preserving legacy compatibility. This approach is suitable when targeting SoC security-by-design for two reasons.…”
Section: Background and Related Workmentioning
confidence: 99%
“…The MARTE standard [3] (Modeling and Analysis of Real-Time and Embedded Systems) offers a methodology for SoC co-design [4], with GASPARD [5] as the SoC co-design environment to move from high-level MARTE specifications to an executable platform. Teodorov [6] has demonstrated regression-free inheritance refactoring while offering additional debugging facilities, These works bring new functionalities (exploration, debugging, automatic generation), while preserving legacy compatibility. This approach is suitable when targeting SoC security-by-design for two reasons.…”
Section: Background and Related Workmentioning
confidence: 99%
“…Ciprian Teodorov et al . addressed physical‐design automation and presented a methodological approach relying on model‐driven engineering. Also, they summarized some lessons learned from the incremental redesign of Madeo , a toolkit that targets field‐programmable gate array design automation.The goal of the IWST workshop series is to create and foster a forum around advances or experiences in Smalltalk.…”
mentioning
confidence: 99%